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MC68HC11A0P Datasheet(PDF) 11 Page - Motorola, Inc |
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MC68HC11A0P Datasheet(HTML) 11 Page - Motorola, Inc |
11 / 45 page MC68HC11A8 MOTOROLA MC68HC11A8TS/D 11 RBOOT, SMOD, and MDA reset depend on conditions at reset and can only be written in special modes (SMOD = 1). RBOOT — Read Bootstrap ROM 0 = Bootloader ROM disabled and not in map 1 = Bootloader ROM enabled and in map at $BF40–$BFFF SMOD —Special Mode Select MDA — Mode Select A IRV — Internal Read Visibility 0 = No internal read visibility on external bus 1 = Data from internal reads is driven out through the external data bus PSEL3–PSEL0 — Priority Select Bits 3 through 0 Refer to 3 Resets and Interrupts. RAM[3:0] —256-Byte Internal RAM Map Position RAM[3:0] determine the upper four bits of the RAM address, positioning RAM at the selected 4K bound- ary. REG[3:0] —64-Byte Register Block Map Position REG[3:0] determine the upper four bits of the register address, positioning registers at the selected 4K boundary. Register can be written only once in the first 64 cycles out of reset in normal modes, or any time in special modes. HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous $103C Bit 7 654321 Bit 0 RBOOT SMOD MDA IRV PSEL3 PSEL2 PSEL1 PSEL0 RESET: ———— 0101 Inputs Mode Latched at Reset MODB MODA RBOOT SMOD MDA 1 0 Single Chip 0 0 0 1 1 Expanded Multiplexed 0 0 1 0 0 Special Bootstrap 1 1 0 0 1 Special Test 0 1 1 INIT — RAM and I/O Mapping $103D Bit 7 654321 Bit 0 RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 RESET: 00000001 |
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