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A3942 Datasheet(PDF) 4 Page - Allegro MicroSystems |
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A3942 Datasheet(HTML) 4 Page - Allegro MicroSystems |
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4 / 20 page  Quad High-Side Gate Driver for Automotive Applications A3942 4 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ. Max. Units Supplies and Regulators Operating Voltage VBB 4.5 – 60 V Quiescent Current IBB(Q) Charge pump on, outputs disabled VBB = 60 V – – 10 mA VBB = 36 V – – 8 mA Sleep mode VBB = 36 V – – 15 μA VBB = 36 V, TJ = 25°C – – 1 μA Logic Supply (voltage supplied to logic circuits) VDD 3 – 5.5 V Logic Supply Current IDD VDD = 5.5 V, serial port switching – – 3 mA VDD = 5.5 V, device quiescent or in sleep mode – – 0.5 mA Logic Supply UVLO Threshold VDD(UV) VDD falling, FAULTZ pin held active (low) for 1.5 V ≤ VDD ≤ VDDUV 2.6 – 2.9 V Logic Supply UVLO Hysteresis VDD(hys) 100 150 200 mV Charge Pump Switching Frequency fCP – 100 – kHz Charge Pump Output Voltage VCP Measured relative to VBB pin VBB = 12 V, ICP = 10 mA 10 – 13 V VBB = 6.0 V, ICP = 5 mA 10 – 13 V VBB = 4.5 V, ICP = 5 mA 7 – 11 V Charge Pump UVLO VCP(UV) Relative to VBB pin, VCP falling 5.1 – 5.8 V Internal Regulator Voltage VREG CREG = 0.22 μF –4– V Regulator Voltage UVLO VREG(UV) VREG falling 3 – 3.8 V Regulator Voltage UVLO Hysteresis VREG(hys) 100 – 400 mV Control Circuits Current Reference Source Voltage VREF 1.14 1.2 1.26 V Master Reset Pulse tRESET RESETZ pin pulsed low 0.3 – 5 μs Sleep Command tSLEEP RESETZ pin held low 20 – – μs Wake-Up Delay tWAKE RESETZ pin held high; CCP = 1 μF ––2 ms Logic I/O Logic Input Voltage, High VIH 0.7 × VDD –VDD V Logic Input Voltage, Low VIL 0– 0.3 × VDD V ELECTRICAL CHARACTERISTICS Valid at –40°C ≤ TJ ≤ 150°C, C12 = C34 = 0.47 μF, CCP = 1 μF, RREF = 60.4 kΩ, and VBB within limits, unless otherwise noted Continued on the next page... |
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