RoboClock
CY7B994V
CY7B993V
Document #: 38-07127 Rev. *E
Page 10 of 14
AC Test Loads and Waveform[26]
Notes:
18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew,
cycle-cycle jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given frequency.
19. Tested initially and after any design or process changes that may affect these parameters.
20. Rise and fall times are measured between 2.0V and 0.8V.
21. fNOM must be within the frequency range defined by the same FS state.
22. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
24. Measured at 0.5V deviation from starting voltage.
25. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz.
26. These figures are for illustrations only. The actual ATE loads may vary.
TTB
Total Timing Budget window (same frequency and phase)[17, 18]
–
500
–
700
ps
tPDDELTA
Propagation Delay difference between two devices[17]
–
200
–
200
ps
tREFpwh
REF input (Pulse Width HIGH)[19]
2.0
–
2.0
–
ns
tREFpwl
REF input (Pulse Width LOW)[19]
2.0
–
2.0
–
ns
tr/tf
Output Rise/Fall Time[20]
0.15
2.0
0.15
2.0
ns
tLOCK
PLL Lock Time From Power-up
–
10
–
10
ms
tRELOCK1
PLL Relock Time (from same frequency, different phase) with Stable
Power Supply
–
500
–
500
µs
tRELOCK2
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply[21]
–
1000
–
1000
µs
tODCV
Output duty cycle deviation from 50%[13]
–1.0
1.0
–1.0
1.0
ns
tPWH
Output HIGH time deviation from 50%[22]
–
1.5–1.5
ns
tPWL
Output LOW time deviation from 50%[22]
–
2.0–2.0
ns
tPDEV
Period deviation when changing from reference to reference[23]
–
0.025
–
0.025
UI
tOAZ
DIS[1:4]/FBDIS HIGH to output high-impedance from ACTIVE[14, 24]
1.0
10
1.0
10
ns
tOAZ
DIS[1:4]/FBDIS LOW to output ACTIVE from output
high-impedance[24, 25]
0.5
14
0.5
14
ns
Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] (continued)
Parameter
Description
CY7B993/4V-2
CY7B993/4V-5
Unit
Min.
Max.
Min.
Max.
2.0V
0.8V
3.3V
GND
2.0V
0.8V
3.3V
OUTPUT
(a) LVTTL AC Test Load
< 1ns
< 1 ns
(b) TTL Input Test Waveform
R1
R2
CL
R1 = 910
Ω
R2 = 910
Ω
CL <30 pF
(Includes fixture and
probe capacitance)
R1 = 100
Ω
R2 = 100
Ω
CL < 25 pF to 185 MHz
For LOCK output only
For all other outputs
or 10 pF at 200 MHz
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
