W48C111-16
PRELIMINARY
2
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:1
24, 23
O
CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2.
PCI1:5
5, 7, 8, 10,
11
O
PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
4
O
Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is controlled by voltage applied to VDDQ3.
48MHz
16
O
48-MHz Output: Fixed clock output at 48 MHz. Output voltage swing is controlled by
voltage applied to VDDQ3. This output does not have the SS feature
CPU_STOP#
18
I
CPU_STOP# input: When brought LOW, clock outputs CPU0:1 are stopped LOW
after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,
clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency).
PCI_STOP#
19
I
PCI_STOP# input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
REF
26
O
Fixed 14.318-MHz Output: Used for various system applications. Output voltage
swing is controlled by voltage applied to VDDQ3.
SEL100/66#
15
I
Frequency Selection Inputs: Select power-up default CPU clock frequency as
shown in Table 1 on page 1.
X1
1
I
Crystal Connection or External Reference Frequency Input: This pin can either
be used as a connection to a crystal or to a reference signal.
X2
2
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
PWR_DWN#
17
I
Power-Down Control: When this input is LOW, device goes into a low-power stand-
by condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completing a full clock cycle (2–3 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
VDDQ3
6, 9, 13, 21,
27
P
Power Connection: Connected to 3.3V supply.
VDDQ2
25
P
Power Connection: Power supply for CPU0:1 output buffer. Connected to 2.5V or
3.3V.
GND
3, 12, 14, 20,
22, 28
G
Ground Connection: Connect all ground pins to the common system ground plane.