W48S111-14
PRELIMINARYPRELIMI-
3
Functional Description
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with input
select pins.
An external 10-k
Ω “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W48S111-14 power-up, the first 2 ms of operation is
used for input logic selection. During this period, the Refer-
ence clock output buffer is three-stated, allowing the output
strapping resistor on the l/O pin to pull the pin and its associ-
ated capacitive clock load to either a logic HIGH or LOW state.
At the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is then latched. Next the output buffer
is enabled, which converts the l/O pin into an operating clock
output. The 2-ms timer is started when VDD reaches 2.0V. The
input bit can only be reset by turning VDD off and then back on
again.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 40
Ω (nominal) which is minimally affected by
the 10-k
Ω strap to ground or V
DD. As with the series termina-
tion resistor, the output strapping resistor should be placed as
close to the l/O pin as possible in order to keep the intercon-
necting trace short. The trace from the resistor to ground or
VDD should be kept less than two inches in length to prevent
system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input pe-
riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W48S111-14
VDD
Clock Load
10 k
Ω
Output
Buffer
(Load Option 1)
10 k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W48S111-14
VDD
Clock Load
R
10 k
Ω
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
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