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DS1236A Datasheet(PDF) 10 Page - Dallas Semiconductor |
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DS1236A Datasheet(HTML) 10 Page - Dallas Semiconductor |
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10 / 20 page  DS1236A 10 of 20 When the RC pin is tied to ground, the DS1236A is designed to interface with NMOS processors which do not have the microamp currents required during a battery backed mode. Grounding the RC pin does, however, continue to support nonvolatile backup of system SRAM memory. Nonvolatile systems incorporating NMOS processors generally require that only the SRAM memory and/or timekeeping functions be battery backed. When the processor is not battery backed (RC = 0), all signals connected from the processor to the DS1236A are disconnected from the backup battery supply, or grounded when system VCC decays below VBAT. In the NMOS processor system, the principal emphasis is placed on giving early warnings with NMI , then providing a continuously active RST and RST signal during power-down while isolating the backup battery from the processor during a loss of VCC. During power-down, NMI will pulse low for a minimum of 200 µs, and then return high. If RC is tied low (NMOS mode), the voltage on NMI will follow VCC until VCC supply decays to VBAT, at which point NMI will enter tri-state (see timing diagram). Also, upon VCC out of tolerance at VCCTP, the RST and RST outputs are driven active and RST will follow VCC as the supply decays. On power-up, RST follows VCC up, RST is held low, and both remain active for tRST after valid VCC. During a power-up from a VCC voltage below VBAT, any detected IN pin levels below VTP are disabled from reaching the NMI pin until VCC rises to VCCTP. As a result, any potential NMI pulse will not be initiated until VCC reaches VCCTP. Removal of an active low level on the NMI pin is controlled by either an internal timeout (when the IN pin is less than VTP), or by the subsequent rise of the IN pin above VTP. The initiation and removal of the NMI signal results in an NMI pulse of 0 µs minimum to 500 µs maximum during power-up, depending on the relative voltage relationship between VCC and the IN pin. As an example, when the IN pin is tied to ground, the internal timeout will result in a pulse of 200 µs minimum to 500 µs maximum. In contrast, if the IN pin is tied to VCCO, NMI will not produce a pulse on power-up. Connecting the RC pin to a high (VCCO) invokes CMOS mode and provides nonvolatile support to both the system SRAM as well as a low power CMOS processor. When using CMOS microprocessors, it is possible to place the microprocessor into a very low-power mode termed the “stop” or “halt” mode. In this state the CMOS processor requires only microamp currents and is fully capable of being battery backed. This mode generally allows the CMOS microprocessor to maintain the contents of internal RAM as well as state control of I/O ports during battery backup. The processor can subsequently be restarted by any of several different signals. To maintain this low-power state, the DS1236A issues no NMI and/or reset signals to the processor until it is time to bring the processor back into full operation. To support the low-power processor battery backed mode (RC = 1), the DS1236A provides a pulsed NMI for early power failure warning. Waiting to initiate a Stop mode until after the NMI pin has returned high will guarantee the processor that no other active NMI or RST/ RST will be issued by the DS1236A until one of two conditions occurs: 1) Voltage on the pin rises above VTP, which activates the watchdog, or 2) VCC cycles below then above VBAT, which also results in an active RST and RST . If VCC does not fall below VCCTP, the processor will be restarted by the reset derived from the watchdog timer as the IN pin rises above VTP. With the RC pin tied to VCCO, RST and RST are not forced active as VCC collapses to VCCTP. The RST is held at a high level via the external battery as VCC falls below battery potential. This mode of operation is intended for applications in which the processor is made nonvolatile with an external source, and allows the processor to power down into a Stop mode as signaled from NMI at an earlier voltage level. The NMI output pin will pulse low for tNMI following a low voltage detect at the IN pin of VTP. Following tNMI, however, NMI will also be held at a high level (VBAT) by the battery as VCC decays below VBAT. On power-up, RST and RST are held inactive until VCC reaches VBAT, then RST and RST are driven active for tRST. If the IN pin falls below VTP during an active reset, the reset outputs will be forced inactive by |
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