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DS1337S Datasheet(PDF) 7 Page - Dallas Semiconductor |
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DS1337S Datasheet(HTML) 7 Page - Dallas Semiconductor |
7 / 13 page DS1337 7 of 13 CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information. ADDRESS MAP The address map for the registers of the DS1337 is shown in Table 1. During a multibyte access, when the address pointer reaches the end of the register space (0Fh) it wraps around to location 00h. On a 2- wire START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read. Table 1. Timekeeper Registers ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE 00H 0 10 Seconds Seconds Seconds 00-59 01H 0 10 Minutes Minutes Minutes 00-59 AM/PM 02H 0 12/24 10hr 10hr Hour Hours 1-12 +AM/PM 00-23 03H 0 0 0 0 0 Day Day 1-7 04H 0 0 10 Date Date Date 00-31 05H Century 0 0 10 Mo Month Month/ Century 01-12 + Century 06H 10 Year Year Year 00-99 07H A1M1 10 Seconds Seconds Alarm 1 Seconds 00-59 08H A1M2 10 Minutes Minutes Alarm 1 Minutes 00-59 AM/PM 09H A1M3 12/24 10hr 10hr Hour Alarm 1 Hours 1-12 + AM/PM 00-23 0AH A1M4 DY/DT 10 DATE Day Date Alarm 1 Day Alarm 1 Date 1-7 1-31 0BH A2M2 10 Minutes Minutes Alarm 2 Minutes 00-59 AM/PM 0CH A2M3 12/24 10hr 10hr Hour Alarm 2 Hours 1-12 + AM/PM 00-23 0DH A2M4 DY/DT 10 Date Day Date Alarm 2 Day Alarm 2 Date 1-7 1-31 0EH EOSC 0 0 RS2 RS1 INTCN A2IE A1IE Control 0FH OSF 0 0 0 0 0 A2F A1F Status Note: Unless otherwise specified, the state of the registers is not defined when power is first applied or VCC falls below the VOSC. |
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