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DS2182A Datasheet(PDF) 8 Page - Dallas Semiconductor

Part # DS2182A
Description  T1 Line Monitor
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2182A Datasheet(HTML) 8 Page - Dallas Semiconductor

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FECR: FRAME ERROR COUNT REGISTER Figure 7
MSB
LSB
FE7
FE6
FE5
FE4
FE3
FE2
FE1
FE0
SYMBOL
POSITION
NAME AND DESCRIPTION
FE7
FECR.7
MSB of frame error count
FFE0
FECR.0
LSB of frame error count
The Frame Error Count Register (FECR) is an 8-bit pre-settable counter that records individual frame bit
errors.
In the 193E mode (RCR2.4 = 1), the FECR records bit errors in the FPS framing pattern
(001011). In the 193S mode (RCR2.4 = 0), the FECR records bit errors in both the FT (101010) and FS
(001110) framing patterns if RCR1.3 is set. If RCR1.3 is cleared, then the FECR only records bit errors in
the FT pattern. This 8-bit counter saturates at 255 and generates an interrupt for each occurrence after
saturation if RIMR2.3 is set. The count is disabled during a loss of sync condition (RLOS = 1).
RSR1: RECEIVE STATUS REGISTER 1 Figure 8
MSB
LSB
8ZD
16ZD
RCL
RYEL
RLOS
B8ZSD
RBL
COFA
SYMBOL
POSITION
NAME AND DESCRIPTION
8ZD
RSR1.7
8 Zero Detect. Set when a string of eight consecutive 0s has
been received at RPOS and RNEG.
16ZD
RSR1.6
16 Zero Detect. Set when a string of 16 consecutive 0s has
been received at RPOS and RNEG.
RCL
RSR1.5
Receive Carrier Loss. Set when a string of 192 consecutive 0s has
been received at RPOS and RNEG. Cleared when 14 or more ones
out of 112 possible bit positions are received.
RYEL
RSR1.4
Receive Yellow Alarm. Set when yellow alarm is detected. The
format of yellow alarm is determined by RCR2.3 and RCR2.4.
RLOS
RSR1.3
Receive Loss of Sync. Set when resync is in progress.
B8ZSD
RSR1.2
B8ZS Code Word Detect. Set when a B8ZS code word is
received at RPOS and RNEG independent of whether the B8ZS
mode is enabled or not (RCR2.2).
RBL
RSR1.1
Receive Blue Alarm. Set when over a 3 ms window, 5 or less
zeros are received. Cleared when over a 3 ms window, 6 or more
zeros are received.
COFA
RSR1.0
Change of Frame Alignment. Set when the last resync resulted in
a change of frame or multiframe alignment.
NOTE:
1. Alarm 8ZD and 16ZD are cleared on the next occurrence of a 1 at RPOS and RNEG.


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