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DS21Q43ATN Datasheet(PDF) 9 Page - Dallas Semiconductor |
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DS21Q43ATN Datasheet(HTML) 9 Page - Dallas Semiconductor |
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9 / 60 page  DS21Q43A 9 of 60 DS21Q43A PIN DESCRIPTION Table 1-4 Transmit Clock [TCLK]. 2.048 MHz primary clock. Used to clock data through the transmit side formatter. Necessary for proper operation of the parallel control port. Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Transmit Channel Clock [TCHCLK]. 256 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of channel data. See Section 11 for timing details. Transmit Bipolar Data [TPOS and TNEG]. Updated on rising edge of TCLK. Can be programmed to output NRZ data on TPOS via the TCR1.7 control bit. Transmit Channel Block [TCHBLK]. A user programmable output that can be forced high or low during any of the 32 E1 channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384 kpbs service (H0), 1920 kpbs (H12), or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications and for per-channel loopback. See Section 11 for timing details. Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled. Should be tied low in applications that do not use the transmit side elastic store. Transmit Link Clock [TLCLK]. 4 kHz to 20 kHz demand clock for the TLINK input. Controlled by TCR2. See Section 11 for timing details. Transmit Link Data [TLINK]. If enabled via TCR2, this pin will be sampled on the falling edge of TCLK to insert data into the Sa bit positions. See Section 11 for timing details. Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the DS21Q43A. Via TCR1.1, the DS21Q43A can be programmed to output either a frame or multiframe pulse at this pin. See Section 11 for timing details. Transmit Frame Sync [TFSYNC]. 8 kHz pulse. Only used when the transmit side elastic store is enabled. A pulse at this pin will establish frame boundaries for the DS21Q43A. Should be tied low in applications that do not use the transmit side elastic store. See Section 11 for timing details. Receive Link Data [RLINK]. Updated with full received E1 data stream on the rising edge of RCLK. See Section 11 for timing details. Receive Link Clock [RLCLK]. 4 kHz to 20 kHz demand clock for the RLINK output. Controlled by RCR2. See Section 11 for timing details. Necessary for proper operation of the parallel control port. Receive Clock [RCLK]. 2.048 MHz primary clock. Used to clock data through the receive side of the framer. Necessary for proper operation of the parallel control port. |
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