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EP20K60E Datasheet(PDF) 6 Page - Altera Corporation |
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EP20K60E Datasheet(HTML) 6 Page - Altera Corporation |
6 / 117 page 6 Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet General Description APEXTM 20K devices are the first PLDs designed with the MultiCore architecture, which combines the strengths of LUT-based and product- term-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for data-path, register- intensive, mathematical, or digital signal processing (DSP) designs. Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines. LUT- and product-term-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20K device architecture uniquely suited for system-on-a-programmable-chip designs. Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20K device. APEX 20KE devices are a superset of APEX 20K devices and include additional features such as advanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry. In addition, APEX 20KE devices extend the APEX 20K family to 1.5 million gates. APEX 20KE devices are denoted with an “E” suffix in the device name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8 compares the features included in APEX 20K and APEX 20KE devices. |
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