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STM6519APARUC6F Datasheet(PDF) 4 Page - STMicroelectronics |
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STM6519APARUC6F Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 25 page List of figures STM6519 4/25 Doc ID 022111 Rev 6 List of figures Figure 1. STM6519 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. UDFN4 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. UDFN6 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. STM6519 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Typical application diagram - input, output and STM6519 device in one voltage domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Typical application diagram - STM6519 device in a different voltage domain than input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Typical application diagram in different voltage domains - SR input in VBAT domain like VCC totally disables the test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. RST output without tREC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9. RST output with tREC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Supply current (ICC) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 11. Smart Reset delay (tSRC) vs. temperature (TA), tSRC = 4.0 s (typ.) . . . . . . . . . . . . . . . . . . 12 Figure 12. Test mode entry voltage (VTEST) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. Initial test mode time (tSRC-INI) vs. temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 14. UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package outline . . . . . . . . . . . . . 17 Figure 15. Footprint recommendation for UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch . . 18 Figure 16. UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package outline . . . . . . . . . . . . . 19 Figure 17. Footprint recommendation for UDFN6 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch. . . 20 Figure 18. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 19. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 20. Package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 |
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