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EP3C40 Datasheet(PDF) 7 Page - Altera Corporation |
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EP3C40 Datasheet(HTML) 7 Page - Altera Corporation |
7 / 14 page Chapter 1: Cyclone III Device Family Overview 1–7 Cyclone III Device Family Architecture July 2012 Altera Corporation Cyclone III Device Handbook Volume 1 Memory Blocks Each M9K memory block of the Cyclone III device family provides nine Kbits of on-chip memory capable of operating at up to 315 MHz for Cyclone III devices and up to 274 MHz for Cyclone III LS devices. The embedded memory structure consists of M9K memory blocks columns that you can configure as RAM, first-in first-out (FIFO) buffers, or ROM. The Cyclone III device family memory blocks are optimized for applications such as high throughout packet processing, embedded processor program, and embedded data storage. The Quartus II software allows you to take advantage of the M9K memory blocks by instantiating memory using a dedicated megafunction wizard or by inferring memory directly from the VHDL or Verilog source code. M9K memory blocks support single-port, simple dual-port, and true dual-port operation modes. Single-port mode and simple dual-port mode are supported for all port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36. True dual-port is supported in port widths with a configuration of ×1, ×2, ×4, ×8, ×9, ×16, and ×18. f For more information about memory blocks, refer to the Memory Blocks in the Cyclone III Device Family chapter. Embedded Multipliers and Digital Signal Processing Support Cyclone III devices support up to 288 embedded multiplier blocks and Cyclone III LS devices support up to 396 embedded multiplier blocks. Each block supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. The Quartus II software includes megafunctions that are used to control the operation mode of the embedded multiplier blocks based on user parameter settings. Multipliers can also be inferred directly from the VHDL or Verilog source code. In addition to embedded multipliers, Cyclone III device family includes a combination of on-chip resources and external interfaces, making them ideal for increasing performance, reducing system cost, and lowering the power consumption of digital signal processing (DSP) systems. You can use Cyclone III device family alone or as DSP device co-processors to improve price-to-performance ratios of DSP systems. The Cyclone III device family DSP system design support includes the following features: ■ DSP IP cores: ■ Common DSP processing functions such as finite impulse response (FIR), fast Fourier transform (FFT), and numerically controlled oscillator (NCO) functions ■ Suites of common video and image processing functions ■ Complete reference designs for end-market applications ■ DSP Builder interface tool between the Quartus II software and the MathWorks Simulink and MATLAB design environments ■ DSP development kits f For more information about embedded multipliers and digital signal processing support, refer to the Embedded Multipliers in Cyclone III Devices chapter. |
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