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EP3CLS200 Datasheet(PDF) 3 Page - Altera Corporation

Part # EP3CLS200
Description  1. Cyclone III Device Family Overview
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

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Chapter 1: Cyclone III Device Family Overview
1–3
Cyclone III Device Family Features
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 1
Wide collection of pre-built and verified IP cores from Altera and Altera
Megafunction Partners Program (AMPP) partners
Supports high-speed external memory interfaces such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM
Auto-calibrating PHY feature eases the timing closure process and eliminates
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
Cyclone III device family supports vertical migration that allows you to migrate your
device to other devices with the same dedicated pins, configuration pins, and power
pins for a given package-across device densities. This allows you to optimize device
density and cost as your design evolves.
Table 1–1 lists Cyclone III device family features.
Table 1–1. Cyclone III Device Family Features
Family
Device
Logic
Elements
Number of
M9K
Blocks
Total RAM
Bits
18 x 18
Multipliers
PLLs
Global
Clock
Networks
Maximum
User I/Os
Cyclone III
EP3C5
5,136
46
423,936
23
2
10
182
EP3C10
10,320
46
423,936
23
2
10
182
EP3C16
15,408
56
516,096
56
4
20
346
EP3C25
24,624
66
608,256
66
4
20
215
EP3C40
39,600
126
1,161,216
126
4
20
535
EP3C55
55,856
260
2,396,160
156
4
20
377
EP3C80
81,264
305
2,810,880
244
4
20
429
EP3C120
119,088
432
3,981,312
288
4
20
531
Cyclone III
LS
EP3CLS70
70,208
333
3,068,928
200
4
20
429
EP3CLS100
100,448
483
4,451,328
276
4
20
429
EP3CLS150
150,848
666
6,137,856
320
4
20
429
EP3CLS200
198,464
891
8,211,456
396
4
20
429


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