OCP,

Open load,

Gate Drive

SCLK

RESET

OUT1

Q

S

R

Q

S

R

OCP

Open

load

From output SR

from output 2

from output 3

from output 4

OCP_FAULT

OPEN_FAULT

25µA

nFAULT

from

other ch.

Overtemp

SDATOUT

1

0

Q

D

CLR

1

0

SDATIN

1

0

1

0

1

0

LD

Q

D

CLR

LD

Q

D

CLR

LD

Q

D

CLR

LD

Q

D

CLR

LATCH

from output register

4.5V

DRV8806

SLVSBA3 – JUNE 2012

www.ti.com

Fault Output Register

The DRV8806 contains circuitry to detect open or shorted loads. The status of the loads can be read via the

serial interface. The logic is shown in Figure 3.

Figure 3. Fault Output

To overcome any leakage currents to accurately sense an open load, a small current source is connected to

each output pin. This source pulls approximately 25-µA of current to ground. The voltage on the output pin is

sensed during the time that the output is off, and if the voltage on the pin is less than 1.2 V (indicating that there

is no load connected) after the open load deglitch time, the OPEN_FAULT latch is set. This latch is cleared

whenever the output bit is set.

When the output is turned on, if an overcurrent (OCP) fault is detected, the channel will be turned off and the

OCP_FAULT latch is set. This latch will be cleared whenever the output bit is cleared.

The state of the OCP_FAULT and OPEN_FAULT signals is combined into a single fault bit per channel, and

loaded into a shift register while the LATCH pin is low. When the LATCH pin is taken high, the fault data is

latched into the shift register at the first falling edge of SCLK. Data may then be shifted out on the SDATOUT pin

on each falling edge of the SCLK pin.

Note that the LATCH signal must be high for a minimum of 200 ns before valid data can be clocked out.

The nFAULT pin will be driven active low whenever any of the OCP_FAULT or OPEN_FAULT latches are set, as

well as whenever there is an overtemperature condition.

8

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