527R-01LF datasheet(1/11 Pages) IDT

Part #	527R-01LF

Description	CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

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DATASHEET

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

ICS527-01

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 1

ICS527-01

REV G 051310

Description

The ICS527-01 Clock Slicer is the most flexible way to

generate an output clock from an input clock with zero

skew. The user can easily configure the device to

produce nearly any output clock that is multiplied or

divided from the input clock. The part supports

non-integer multiplications and divisions. A SYNC

pulse indicates when the rising clock edges are aligned

with zero skew. Using Phase-Locked Loop (PLL)

techniques, the device accepts an input clock up to 200

MHz and produces an output clock up to 160 MHz.

The ICS527-01 aligns rising edges on ICLK and FBIN

at a ratio determined by the reference and feedback

dividers.

For configurable clocks that do not require zero delay,

use the ICS525.

Features

• Packaged as 28-pin SSOP (150 mil body)

• Synchronizes fractional clocks rising edges

• Pin configurable multiplication/division ratio

• Slices frequency or period

• SYNC pulse output indicates aligned edges

• Input clock frequency of 600 kHz to 200 MHz

• Output clock frequencies up to 160 MHz

• Very low jitter

• Duty cycle of 45/55 up to 160 MHz

• Operating voltage of 3.3V

• Pin selectable drive strength

• Multiple outputs available when combined with

fanout buffers

• Industrial temperature version available

• Pb (lead) free package

Block Diagram

ICLK

2xDRIVE

CLK1

CLK2

Reference

Divider

PLL

7

72

R6:R0

F6:F0

S1:S0

PDTS

Feedback

Divider

FBIN

1

0

Divide

by 2

SYNC

DIV2

Feedback can

come from

CLK1 or CLK2

(not both)

PDTS

OECLK2

PDTS

2

GND

2

VDD

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527R-01LF Datasheet(PDF) 1 Page - Integrated Device Technology

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