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527R-01LFT Datasheet(PDF) 2 Page - Integrated Device Technology |
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527R-01LFT Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 11 page ICS527-01 CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 2 ICS527-01 REV G 051310 Pin Assignment 28 pin 150 mil body SSOP Frequency Range Table To cover the range from 10 to 18 MHz (0 to 70°C) and 8 to 16 MHz (-40 to 85°C), select address 01 to generate 2x your desired output frequency, then configure CLK2 to generate CLK1/2. Pin Descriptions 18 7 17 8 16 9 15 ICLK 10 FBIN 11 GND 12 CLK2 13 OECLK2 14 2XDRIVE GND PDTS F6 F0 F5 F3 F1 F4 22 21 20 19 F2 CLK1 5 6 S1 VDD VDD 24 23 R0 3 4 DIV2 S0 R1 26 25 R2 1 2 R5 R6 R3 28 27 R4 S1 S0 CLK1 Output Frequency (MHz) Commercial (0 to 70°C) Industrial (-40 to 85°C) 0 0 37 - 75 35 - 70 0 1 18 - 37 16 - 35 1 0 4 - 10 4 - 8 1 1 75 -160 70 - 140 CLK2 Operation Table OECLK2 DIV2 CLK2 0X Z 1 0 SYNC 11 CLK1/2 CLK Drive Select Table 2XDRIVE Output Drive 0 12 mA 1 25 mA Pin Number Pin Name Pin Type Pin Description 1,2, 24-28 R5, R6, R0-R4 Input Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up resistor. 3 DIV2 Input Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based on the table above. Internal pull-up resistor. 4, 5 S0, S1 Input Select pins for output divider determined by user. See table above. Internal pull-up resistor. 6, 23 VDD Power Connect to VDD. 7 ICLK Input Reference clock input. 8 FBIN Input Feedback clock input. 9, 20 GND Power Connect to ground. 10 OECLK2 Input CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up resistor. 11 2XDRIVE Input Clock output drive strength doubled when high. Internal pull-up resistor. 12-18 F0-F6 Input Feedback divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up resistor. 19 PDTS Input Power Down. Active low. Turns off entire chip when low, both clock outputs are tri-stated. Internal pull-up resistor. 21 CLK2 Output Output clock 2. Can be SYNC output or a low skew divide by 2 of CLK1. 22 CLK1 Output Output clock 1. |
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