ICS527-01

CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 9

ICS527-01

REV G 051310

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85

° C

Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.

External Components

The ICS527-01 requires two 0.01 µF decoupling capacitors to be connected between VDD and GND, one

on each side of the chip. They must be connected close to the device to minimize lead inductance. No

external power supply filtering is required for this device. A 33

Ω series terminating resistor should be used

on the CLK1 and CLK2 output pins.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

0.6

200

MHz

Output Frequency, CLK1

0 to +70

° C4

160

MHz

-40 to +85

° C4

140

MHz

CLK1 Frequency for Correct

SYNC Operation

66

MHz

Output Rise Time

0.8 to 2.0 V

1

ns

Output Fall Time

2.0 to 0.8 V

1

ns

Output Clock Duty Cycle

Measured at VDD/2,

45

50

55

%

Power Down Time, PDTS low to

clocks tri-stated

50

ns

Power Up Time, PDTS high to

clocks stable

10

ms

Absolute Clock Period Jitter

Deviation from mean

± 90

ps

One sigma Clock Period Jitter

40

ps

Skew of Output Clocks

CLK1 to CLK2, Note 1

-250

250

ps

Input Capacitance

4pF

Input to Output Skew

ICLK to FBIN, Note 1

-250

250

ps

Device to Device Skew

Common ICLK, at FBIN

0

500

ps