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C8051F560-IQ Datasheet(PDF) 8 Page - Silicon Laboratories |
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C8051F560-IQ Datasheet(HTML) 8 Page - Silicon Laboratories |
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8 / 303 page  C8051F55x/56x/57x 8 Rev. 1.1 List of Figures Figure 1.1. C8051F568-9 and ‘F570-5 (40-pin) Block Diagram .............................. 17 Figure 1.2. C8051F560-7 (32-pin) Block Diagram ................................................... 18 Figure 1.3. C8051F550-7 (24-pin) Block Diagram ................................................... 19 Figure 3.1. QFN-40 Pinout Diagram (Top View) ..................................................... 24 Figure 3.2. QFP-32 Pinout Diagram (Top View) ...................................................... 25 Figure 3.3. QFN-32 Pinout Diagram (Top View) ..................................................... 26 Figure 3.4. QFN-24 Pinout Diagram (Top View) ..................................................... 27 Figure 4.1. QFN-40 Package Drawing .................................................................... 28 Figure 4.2. QFN-40 Landing Diagram ..................................................................... 29 Figure 4.3. QFP-32 Package Drawing ..................................................................... 30 Figure 4.4. QFP-32 Landing Diagram ..................................................................... 31 Figure 4.5. QFN-32 Package Drawing .................................................................... 32 Figure 4.6. QFN-32 Landing Diagram ..................................................................... 33 Figure 4.7. QFN-24 Package Drawing .................................................................... 34 Figure 4.8. QFN-24 Landing Diagram ..................................................................... 35 Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency ........... 39 Figure 6.1. ADC0 Functional Block Diagram ........................................................... 47 Figure 6.2. ADC0 Tracking Modes .......................................................................... 49 Figure 6.3. 12-Bit ADC Tracking Mode Example ..................................................... 50 Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4 ............. 51 Figure 6.5. ADC0 Equivalent Input Circuit ............................................................... 53 Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 64 Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 64 Figure 6.8. ADC0 Multiplexer Block Diagram .......................................................... 65 Figure 6.9. Temperature Sensor Transfer Function ................................................ 67 Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 68 Figure 8.1. Comparator Functional Block Diagram ................................................. 70 Figure 8.2. Comparator Hysteresis Plot .................................................................. 71 Figure 8.3. Comparator Input Multiplexer Block Diagram ........................................ 76 Figure 9.1. External Capacitors for Voltage Regulator Input/Output— Regulator Enabled ................................................................................ 79 Figure 9.2. External Capacitors for Voltage Regulator Input/Output— Regulator Disabled ................................................................................ 80 Figure 10.1. CIP-51 Block Diagram ......................................................................... 82 Figure 11.1. C8051F55x/56x/57x Memory Map ...................................................... 92 Figure 11.2. Flash Program Memory Map ............................................................... 93 Figure 12.1. SFR Page Stack .................................................................................. 96 Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT ... 97 Figure 12.3. SFR Page Stack After CAN0 Interrupt Occurs .................................... 98 Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR . 99 Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 100 Figure 12.6. SFR Page Stack Upon Return From CAN0 Interrupt ........................ 101 Figure 14.1. Flash Program Memory Map ............................................................. 126 |
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