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ZSPM9000AI1R Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # ZSPM9000AI1R
Description  Ultra-Compact, High-Performance DrMOS Device
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ZSPM9000
Ultra-Compact, High-Performance DrMOS Device
Data Sheet
March 12, 2012
© 2012 Zentrum Mikroelektronik Dresden AG
— Rev.1.01
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is subject to changes without
notice.
5 of 27
Figure 1.16 Disable Thresholds vs. Driver Supply Voltage.....................................................................................12
Figure 1.17 Disable Thresholds vs. Temperature ...................................................................................................12
Figure 1.18 Disable Pull-Down Current vs. Temperature .......................................................................................12
Figure 2.1
Typical Application Circuit with PWM Control......................................................................................13
Figure 2.2
ZSPM9000 Block Diagram...................................................................................................................14
Figure 2.3
THWN# Operation ...............................................................................................................................15
Figure 2.4
PWM and Tri-state Timing Diagram ....................................................................................................16
Figure 2.5
SMOD# Timing Diagram......................................................................................................................18
Figure 2.6
PWM Timing ........................................................................................................................................19
Figure 3.1
Power Loss Measurement Block Diagram...........................................................................................21
Figure 4.1
Pin-out PQFN40 Package....................................................................................................................22
Figure 4.2
PQFN40 Physical Dimensions and Recommended Footprint .............................................................24
Figure 5.1
PCB Layout Example...........................................................................................................................26
List of Tables
Table 2.1
UVLO and Disable Logic......................................................................................................................14
Table 2.2
SMOD# Logic.......................................................................................................................................17


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