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EP5382QI Datasheet(PDF) 9 Page - Altera Corporation |
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EP5382QI Datasheet(HTML) 9 Page - Altera Corporation |
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9 / 18 page  EP5382QI/EP5362QI/EP5352QI Output Voltage Select To provide the highest degree of flexibility in choosing output voltage, the EP53x2QI family uses a 3 pin VID, or Voltage ID, output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to use an external voltage divider. Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. Table 1 shows the various VS0-VS2 pin logic states and the associated output voltage levels. A logic “1” indicates a connection to VIN or to a “high” logic voltage level. A logic “0” indicates a connection to ground or to a “low” logic voltage level. These pins can be either hardwired to VIN or GND or alternatively can be driven by standard logic levels. These pins must not be left floating. VS2 VS1 VS0 VOUT 0 0 0 3.3 0 0 1 2.5 0 1 0 2.8 0 1 1 1.2 1 0 0 3.0 1 0 1 1.8 1 1 0 2.7 1 1 1 External External Voltage Divider As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins to VIN or logic “high”. The EP53x2QI uses a separate feedback pin, VFB, when using the external divider. VSENSE must be connected to VOUT as indicated in Figure 5. VIN VSense Vin VS1 VS2 VS0 10 µF 2.2uF 4.7uF VOUT Vout GND ENABLE Ra Rb VFB Figure 5. External Divider. The output voltage is selected by the following formula: ( ) Rb Ra OUT V V + = 1 603 . 0 Ra must be chosen as 200KΩ to maintain loop gain. Then Rb is given as: Ω − = 603 . 0 10 2 . 1 5 OUT b V x R Dynamically Adjustable Output The EP53x2QI are designed to allow for dynamic switching between the predefined VID voltage levels The inter-voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. The slew rate is identical to the soft- start slew rate of 3V/mS. Dynamic transitioning between internal VID settings and the external divider is not allowed. Power-Up/Down Sequencing During power-up, ENABLE should not be asserted before VIN. During power down, the VIN should not be powered down before the ENABLE. Tying PVIN and ENABLE together Table 1. Voltage select settings. 9 www.altera.com/enpirion 03132 October 11, 2013 Rev H |
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