EP5382QI/EP5362QI/EP5352QI

Recommendation 3: Multiple small vias (0.25mm after copper plating) should be used to connect

ground terminals of the Input capacitor and the output capacitor to the system ground plane. This

provides a low inductance path for the high-frequency AC currents, thereby reducing ripple and

suppressing EMI (see Fig. 5, Fig. 6, and Fig. 7).

Recommendation 4: The large thermal pad underneath the component must be connected to the

system ground plane through as many thermal vias as possible. The vias should use 0.33mm drill

size with minimum one ounce copper plating (0.035mm plating thickness). This provides the path for

heat dissipation from the converter.

Recommendation 5: The system ground plane referred to in recommendations 3 and 4 should be

the first layer immediately below the surface layer (PCB layer 2).

This ground plane should be

continuous and un-interrupted below the converter and the input and output capacitors that carry

large AC currents.

If it is not possible to make PCB layer 2 a continuous ground plane, an

uninterrupted ground “island” should be created on PCB layer 2 immediately underneath the

EP53x2QI and its input and output capacitors. The vias that connect the input and output capacitor

grounds, and the thermal pad to the ground island, should continue through to the PCB GND layer as

well.

Recommendation 6: As with any switch-mode DC/DC converter, do not run sensitive signal or

control lines underneath the converter package.

Figure 6 shows an example schematic for the EP53x2QI using the internal voltage select. In this

NC

NC

NC

V

OUT

ENABLE

VS0

VS1

VS2

10

9

8

7

20

19

18

17

4.7uF/2.2uF

10

µF

V

IN

V

OUT

(see layout recommendation 3)

Figure 6. Example application, Vout=1.2V.

Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The

resistor values are chosen to give an output voltage of 2.6V.

11

www.altera.com/enpirion

03132

October 11, 2013

Rev H