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UESD6V8L4A Datasheet(PDF) 5 Page - Union Semiconductor, Inc. |
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UESD6V8L4A Datasheet(HTML) 5 Page - Union Semiconductor, Inc. |
5 / 10 page ________________________________________________________________________ http://www.union-ic.com Rev.02 Jul.2012 5/10 UESD6V8Lxx Application Information UESD6V8Lxx can use as unidirectional lines or bidirectional lines protector. For example, UESD6V8L4B can use as a four unidirectional lines protector, and also can use as a three bidirectional lines protector (as figure1 shows). For bidirectional applications, the junction capacitance between I/O ports and ground is half of the single TVS’s junction capacitance, that is to say the typical value of the junction capacitance between I/O ports and ground is 6pF. The break down voltage of these two series connection TVS is a forwards voltage (about 0.7V) higher than a single TVS’s. Figure1: UESD6V8L4B use as three bidirectional lines protector Circuit Board Layout Recommendations for Suppression of ESD Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: 1. Place the TVS near the input terminals or connectors to restrict transient coupling. 2. Minimize the path length between the TVS and the protected line. 3. Minimize all conductive loops including power and ground loops. 4. The ESD transient return path to ground should be kept as short as possible. 5. Never run critical signals near board edges. 6. Use ground planes whenever possible. For multilayer printed-circuit boards, use ground vias. 7. Keep parallel signal paths to a minimum. 8. Avoid running protection conductors in parallel with unprotected conductor. 9. Minimize all printed-circuit board conductive loops including power and ground loops. 10. Avoid using shared transient return paths to a common ground point. |
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