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EP1C3 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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EP1C3 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 385 page Altera Corporation vii Preliminary Contents 1.8-V LVTTL Normal and Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) ..... 8–4 1.8-V LVCMOS Normal and Wide Voltage Ranges (EIA/JEDEC Standard EIA/JESD8-7) . 8–4 1.5-V LVCMOS Normal and Wide Voltage Ranges (EIA/JEDEC Standard JESD8-11) ........ 8–5 3.3-V (PCI Special Interest Group (SIG) PCI Local Bus Specification Revision 2.2) ............... 8–5 SSTL-3 Class I and II (EIA/JEDEC Standard JESD8-8) ............................................................... 8–7 SSTL-2 Class I and II (EIA/JEDEC Standard JESD8-9A) ........................................................... 8–7 LVDS (ANSI/TIA/EIA Standard ANSI/TIA/EIA-644) ............................................................ 8–8 Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A ............................................................... 8–9 Cyclone I/O Banks ................................................................................................................................ 8–9 Programmable Current Drive Strength ............................................................................................ 8–12 Hot Socketing ....................................................................................................................................... 8–13 I/O Termination .................................................................................................................................. 8–13 Voltage-Referenced I/O Standard Termination ........................................................................ 8–14 Differential I/O Standard Termination ...................................................................................... 8–14 Pad Placement and DC Guidelines ................................................................................................... 8–14 Differential Pad Placement Guidelines ....................................................................................... 8–14 VREF Pad Placement Guidelines ................................................................................................... 8–15 DC Guidelines ................................................................................................................................. 8–18 Quartus II Software Support .............................................................................................................. 8–18 Settings ............................................................................................................................................. 8–18 Conclusion ............................................................................................................................................ 8–22 More Information ................................................................................................................................ 8–22 References ............................................................................................................................................. 8–22 Referenced Documents ....................................................................................................................... 8–23 Document Revision History ............................................................................................................... 8–23 Chapter 9. High-Speed Differential Signaling in Cyclone Devices Introduction ............................................................................................................................................ 9–1 Cyclone High-Speed I/O Banks .......................................................................................................... 9–2 Cyclone High-Speed I/O Interface ..................................................................................................... 9–3 Clock Domains .................................................................................................................................. 9–3 LVDS Receiver and Transmitter .......................................................................................................... 9–4 RSDS I/O Standard Support in Cyclone Devices ............................................................................. 9–7 Designing with RSDS ....................................................................................................................... 9–9 RSDS Software Support ................................................................................................................. 9–10 High-Speed I/O Timing in Cyclone Devices .................................................................................. 9–11 LVDS Receiver and Transmitter Termination ................................................................................. 9–15 Implementing Cyclone LVDS and RSDS I/O Pins in the Quartus II Software .......................... 9–16 Design Guidelines ............................................................................................................................... 9–18 Differential Pad Placement Guidelines ....................................................................................... 9–18 Board Design Considerations ....................................................................................................... 9–18 Conclusion ............................................................................................................................................ 9–19 Referenced Documents ....................................................................................................................... 9–19 Document Revision History ............................................................................................................... 9–20 |
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