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EPF81500AQC240-2 Datasheet(PDF) 7 Page - Altera Corporation |
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EPF81500AQC240-2 Datasheet(HTML) 7 Page - Altera Corporation |
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7 / 62 page  Altera Corporation 7 FLEX 8000 Programmable Logic Device Family Data Sheet 3 Each LAB provides four control signals that can be used in all eight LEs. Two of these signals can be used as clocks, and the other two for clear/preset control. The LAB control signals can be driven directly from a dedicated input pin, an I/O pin, or any internal signal via the LAB local interconnect. The dedicated inputs are typically used for global clock, clear, or preset signals because they provide synchronous control with very low skew across the device. FLEX 8000 devices support up to four individual global clock, clear, or preset control signals. If logic is required on a control signal, it can be generated in one or more LEs in any LAB and driven into the local interconnect of the target LAB. Logic Element The logic element (LE) is the smallest unit of logic in the FLEX 8000 architecture, with a compact size that provides efficient logic utilization. Each LE contains a 4-input LUT, a programmable flipflop, a carry chain, and cascade chain. Figure 3 shows a block diagram of an LE. Figure 3. FLEX 8000 LE The LUT is a function generator that can quickly compute any function of four variables. The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flipflop can be driven by dedicated input pins, general-purpose I/O pins, or any internal logic. For purely combinatorial functions, the flipflop is bypassed and the output of the LUT goes directly to the output of the LE. LABCTRL3 LABCTRL4 DATA1 DATA2 DATA3 DATA4 LABCTRL1 LABCTRL2 Carry-In LE-Out Clock Select Carry-Out PRN CLRN DQ DFF Look-Up Table (LUT) Clear/ Preset Logic Carry Chain Cascade Chain Cascade-In Cascade-Out |
Similar Part No. - EPF81500AQC240-2 |
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Similar Description - EPF81500AQC240-2 |
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