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LTC2158-12 Datasheet(PDF) 9 Page - Linear Dimensions Semiconductor |
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LTC2158-12 Datasheet(HTML) 9 Page - Linear Dimensions Semiconductor |
9 / 28 page 9 215812f LTC2158-12 SDI(Pin60):SerialInterfaceDataInput.Inserialprogram- ming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel pro- gramming mode (PAR/SER = VDD), SDI selects 3.5mA or 1.75mA LVDS output current (see Table 2). SDI can be driven with 1.8V to 3.3V logic. SCK (Pin 61): Serial Interface Clock Input. In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK can be used to place the part in the low power sleep mode (see Table 2). SCK can be driven with 1.8V to 3.3V logic. CS (Pin 62): Serial Interface Chip Select Input. In serial programming mode, (PAR/SER = 0V), CS is the serial in- terface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS controls the clock duty cycle stabilizer (see Table 2). CS can be driven with 1.8V to 3.3V logic. PAR/SER (Pin 63): Programming Mode Selection Pin. Connecttogroundtoenabletheserialprogrammingmode where CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to en- able the parallel programming mode where CS, SCK, SDI become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. LVDS Outputs The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 100Ω termination resistor between the pins of each LVDS output pair. OF–/OF+ (Pins 22/23): Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred. The overflows for channel A and channel B are multiplexed together. DB0_1–/DB0_1+ to DB10_11–/DB10_11+ (Pins 26/27, 28/29, 30/31, 34/35, 36/37, 38/39): Channel B Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differentialoutputpair.Theevendatabits(DB0,DB2,DB4, DB6, DB8, DB10) appear when CLKOUT+ is low. The odd data bits (DB1, DB3, DB5, DB7, DB9, DB11) appear when CLKOUT+ is high. CLKOUT–/CLKOUT+ (Pins 40/41): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. DA0_1–/DA0_1+ to DA10_11–/DA10_11+ (Pins 44/45, 46/47, 50/51, 52/53, 54/55, 56/57): Channel A Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differentialoutputpair.Theevendatabits(DA0,DA2,DA4, DA6, DA8, DA10) appear when CLKOUT+ is low. The odd data bits (DA1, DA3, DA5, DA7, DA9, DA11) appear when CLKOUT+ is high. pin FuncTions |
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