78A2GC8AF00C datasheet(1/7 Pages) ETC2

Part #	78A2GC8AF00C

Description	2GB DDR3 SDRAM SODIMM with SPD

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Manufacturer	ETC2 [List of Unclassifed Manufacturers]

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Specifications

Features

•

On Dimm Thermal Sensor: No

• Double-data-rate architecture; two data transfers per

• Density: 2GB

clock cycle

• Organization

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

 256M words × 64 bits, 1 rank

• Bi-directional differential data strobe (DQS and /DQS)

• Mounting 8 pieces of 2G bits DDR3 SDRAM sealed

is transmitted/received with data for capturing data at

in FBGA

the receiver

• Package: 204-pin socket type small outline dual in

• DQS is edge-aligned with data for READs; center-

line memory module (SO-DIMM)

aligned with data for WRITEs

 PCB height: 30.0mm

• Differential clock inputs (CK and /CK)

 Lead pitch: 0.6mm (pin)

• DLL aligns DQ and DQS transitions with CK

 Lead-free (RoHS compliant)

transitions

• Power supply: VDD = 1.5V ± 0.075V

• Commands entered on each positive CK edge; data

• Eight internal banks for concurrent operation

and data mask referenced to both edges of DQS

(components)

• Data mask (DM) for write data

• Interface: SSTL_15

• Posted /CAS by programmable additive latency for

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

better command and data bus efficiency

• /CAS Latency (CL): 6, 7, 8, 9

• On-Die-Termination (ODT) for better signal quality

• /CAS write latency (CWL): 5, 6, 7

 Synchronous ODT

• Precharge: auto precharge option for each burst

 Dynamic ODT

access

 Asynchronous ODT

• Refresh: auto-refresh, self-refresh

• Multi Purpose Register (MPR) for temperature read

• Refresh cycles

out

 Average refresh period

• ZQ calibration for DQ drive and ODT

7.8µs at 0°C ≤ TC ≤ +85°C

• Programmable Partial Array Self-Refresh (PASR)

3.9µs at +85°C < TC ≤ +95°C

• /RESET pin for Power-up sequence and reset

• Operating case temperature range

function

 TC = 0°C to +95°C

• SRT range:

 Normal/extended

 Auto/manual self-refresh

• Programmable Output driver impedance control

Apacer Memory Product Specification

2GB DDR3 SDRAM SODIMM with SPD

Ordering Information

Part Number

Bandwidth Speed Grade

Max Frequency

CAS Latency

Density Organization

Component

Composition

Number of

Rank

78.A2GC8.AF00C

2GB

256Mx64

256Mx8*8EA

1

8.5GB/sec

1066Mbps

533MHz

CL7

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