BELASIGNA 250

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8

Pad Index

A/D

I/O

Description

BELASIGNA 250 Pin Name

A4

SPI_SERI

SPI serial input

I

D

E6

TWSS_CLK

Two−wire synchronous serial clock

I/O

D

F8

TWSS_DATA

Two−wire synchronous serial data

I/O

D

G5

GPIO[0] / I2S_FD

General−purpose input or output / I2S digital frame

I/O

D

H5

GPIO[1] / I2S_IND

General−purpose input or output / I2S digital input

I/O

D

G4

GPIO[2] / I2S_INA

General−purpose input or output / I2S analog input

I/O

D

F5

GPIO[3] / NCLK_DIV_RESET / I2S_FA

General−purpose input or output / I2S analog frame

I/O

D

B5

GPIO[4] / LSAD [0] / I2S_OUTD

General−purpose input or output / low−speed A/D input /

I2S digital output

I/O

D/A

A5

GPIO[5] / LSAD[1] / I2S_OUTA

General−purpose input or output / low−speed A/D input /

I2S analog output

I/O

D/A

B6

GPIO[6] / LSAD[2]

General−purpose input or output / low−speed A/D input

I/O

D/A

A7

GPIO[7] / LSAD[3]

General−purpose input or output / low−speed A/D input

I/O

D/A

A8

GPIO[8] / LSAD[4] / UART_TX

General−purpose input or output / low−speed A/D input /

UART output

I/O

D/A

B7

GPIO[9] / LSAD[5] / UART_RX

General−purpose input or output / low−speed A/D input /

UART input

I/O

D/A

B8

GPIO[10] / UCLK

General−purpose input or output / user clock

I/O

D

C7

GPIO[11] / PCM_CLK

General−purpose input or output / PCM clock

I/O

D

C8

GPIO[12] / PCM_SERI

General−purpose input or output / PCM serial input

I/O

D

D7

GPIO[13] / PCM_SERO

General−purpose input or output / PCM serial output

I/O

D

D8

GPIO[14] / PCM_FRAME

General−purpose input or output / PCM frame

I/O

D

E7

GPIO[15]

General−purpose input or output

I/O

D

NOTE: Unlisted pads must be left unconnected.

Weight

BELASIGNA 250 LFBGA (0W888−002−XTP) has an average weight of 0.1275 grams.

A total of 49 active pins are present on this CABGA package of BELASIGNA 250. A description of these pads is given in

Table 4.

Table 4. CABGA PIN DESCRIPTIONS

Pad Index

BELASIGNA 250 Pad Name

Description

I/O

A/D

H7

VBAT

Power supply

I

A

H5, J6, H6

AGND

Analog ground

N/A

A

H8

RCVRBAT

Digital output power supply

I

A

G8

RCVRGND

Digital output ground

N/A

A

D9, C3

VDDC

Digital core power supply

O

D

C8

GNDC

Digital core ground

N/A

D

J5

VREG

Regulated microphone power supply

O

A

J1

VDBL

Doubled voltage output

O

A

F1

SPI_CS

SPI chip select

O

D

G2

SPI_CLK

SPI Clock

O

D

F2

SPI_SERO

SPI serial output

O

D

E1

SPI_SERI

SPI serial input

I

D