AP-SDMxxxx1PAXS-EM

8

© 2010 Apacer Technology Inc.

Rev. 1.1

3. Flash Management

3.1

Error Correction/Detection

The SDM implements a hardware ECC scheme, based on the BCH algorithm, to achieve up to 8/15 bit

correction per 512 bytes.

3.2

Bad Block Management

Although bad blocks on the flash media are already identified by the flash manufacturer, they can also be

accumulated over time during operation. The controller of SDM maintains a table that lists those normal

blocks with disk data, the free blocks for wear leveling, and bad blocks with errors. When a normal block is

detected broken, it is replaced with a free block and listed as a bad block. When a free block is detected

broken, it is then removed from the free block list and marked as a bad block.

During device operation, this ensures that newly accumulated bad blocks are transparent to the host. The

device will stop file write service once there are only two free blocks left such that the read function is still

available for copying the files from the disk into another.

3.3

Wear Leveling

The NAND flash devices are limited by a certain number of write cycles. When using a FAT-based file system,

frequent FAT table updates are required. If some area on the flash wears out faster than others, it would

significantly reduce the lifetime of the whole SSD, even if the erase counts of others are far from the write

cycle limit. Thus, if the write cycles can be distributed evenly across the media, the lifetime of the media can

be prolonged significantly. This scheme is called wear leveling.

Apacer’s wear-leveling scheme is achieved both via buffer management and Apacer-specific global wear

leveling. They both ensure that the lifetime of the flash media can be increased, and the disk access

performance is optimized as well.

3.4

Power Failure Management

The Low Power Detection on the controller initiates cached data saving before the power supply to the device

is too low. This feature prevents the device from crash and ensures data integrity during an unexpected

blackout. Once power was failure before cached data writing back into flash, data in the cache will lost. The

next time the power is on, the controller will check these fragmented data segment, and, if necessary, replace

them with old data kept in flash until programmed successfully.

3.5

Quick Erase

Accomplished by the Secure Erase (SE) command, which added to the open ANSI standards that control disk

drives, “Quick Erase” is built into the disk drive itself and thus far less susceptible to malicious software

attacks than external software utilities. It is a positive easy-to-use data destroy command, amounting to

electronic data shredding. Executing the command causes a drive to internally completely erase all possible

user data. This command is carried out within disk drives, so no additional software is required. Once

executed, neither data nor the erase counter on the device would be recoverable, which blurs the accuracy of