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CS4207-CNZ Datasheet(PDF) 3 Page - Cirrus Logic |
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3 / 148 page DS880F4 3 CS4207 TABLE OF CONTENTS 1. PIN DESCRIPTIONS .............................................................................................................................. 8 1.1 CS4207 48-pin QFN Pinout: ............................................................................................................ 8 1.2 Digital I/O Pin Characteristics ........................................................................................................ 10 2. TYPICAL CONNECTION DIAGRAMS .................................................................................................11 3. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13 RECOMMENDED OPERATING CONDITIONS .................................................................................. 13 ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 13 ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) ......................................................... 14 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ......................................................... 15 ADC DIGITAL FILTER CHARACTERISTICS ...................................................................................... 16 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ..................................................... 17 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ..................................................... 19 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................. 21 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 21 DIGITAL MICROPHONE INTERFACE CHARACTERISTICS ............................................................. 22 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS .................................................... 23 HD AUDIO BUS SPECIFICATIONS & CHARACTERISTICS .............................................................. 23 S/PDIF TRANSMITTER/RECEIVER SPECIFICATIONS & CHARACTERISTICS .............................. 23 POWER CONSUMPTION ................................................................................................................... 24 4. CODEC RESET AND INITIALIZATION ............................................................................................... 25 4.1 Link Reset ...................................................................................................................................... 25 4.2 Function Group Reset .................................................................................................................... 25 4.3 Codec Initialization ......................................................................................................................... 25 4.4 D3 Lower Power State Support ..................................................................................................... 26 4.5 Extended Power States Supported (EPSS) ................................................................................... 26 4.6 Power State Settings Reset (PS-SettingsReset) ........................................................................... 28 4.7 Register Settings Across Resets ................................................................................................... 29 5. PRESENCE DETECTION ..................................................................................................................... 31 5.1 Jack Detection Circuit .................................................................................................................... 31 5.1.1 Presence Detection and Unsolicited Response .................................................................... 31 5.1.2 S/PDIF Receiver Presence Detect ........................................................................................ 32 6. HD AUDIO CODEC SUPPORTED VERBS AND RESPONSES ......................................................... 33 6.1 Software Programming Model ....................................................................................................... 33 6.1.1 Node ID Summary ................................................................................................................. 34 6.1.2 Pin Configuration Register Defaults ......................................................................................35 6.2 Root Node (Node ID = 00h) ........................................................................................................... 36 6.2.1 Vendor and Device ID ........................................................................................................... 36 6.2.2 Revision ID ............................................................................................................................ 36 6.2.3 Subordinate Node Count ....................................................................................................... 36 6.3 Audio Function Group (Node ID = 01h) ......................................................................................... 37 6.3.1 Subordinate Node Count ....................................................................................................... 37 6.3.2 Function Group Type ............................................................................................................. 37 6.3.3 Audio Function Group Capabilities ........................................................................................37 6.3.4 Supported PCM Size, Rates ................................................................................................. 38 6.3.5 Supported Stream Formats ................................................................................................... 39 6.3.6 Supported Power States ....................................................................................................... 39 6.3.7 GPIO Capabilities .................................................................................................................. 40 6.3.8 Power States ......................................................................................................................... 41 6.3.9 GPIO Data ............................................................................................................................. 42 6.3.10 GPIO Enable Mask .............................................................................................................. 43 6.3.11 GPIO Direction .................................................................................................................... 43 6.3.12 GPIO Sticky Mask ............................................................................................................... 43 |
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