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MAX823SEXK Datasheet(PDF) 4 Page - Micrel Semiconductor |
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MAX823SEXK Datasheet(HTML) 4 Page - Micrel Semiconductor |
4 / 14 page Micrel, Inc. MAX823/4/5 January 14, 2014 4 Revision 1.0 Pin Configuration MAX823 SOT23(EUK) &SC70(EXK) Top View MAX824 SOT23(EUK) &SC70(EXK) Top View MAX825 SOT23(EUK) &SC70(EXK) Top View Pin Description Pin Number MAX823 Pin Number MAX824 Pin Number MAX825 Pin Name Pin Function 1 1 1 /RESET Active-Low Reset Output. Pulses low for 200ms when triggered, and remains low whenever VCC is below the reset threshold or when /MR is a logic low. It remains low for 200ms after one of the following occurs: VCC rises above the reset threshold, the watchdog triggers a reset, or /MR goes low to high. 2 2 2 GND Ground. - 3 3 RESET Active-High Reset Output. Pulses high for 200ms when triggered, and remains high whenever VCC is below the reset threshold or when /MR is a logic low. It remains high for 200ms after one of the following occurs: VCC rises above the reset threshold, the watchdog triggers a reset, or /MR goes low to high. RESET is the inverse of /RESET. 4 4 - WDI Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and a reset is triggered. The internal watchdog timer clears whenever reset is asserted, or whenever WDI sees a rising or falling edge. If WDI is left unconnected or is connected to a three-stated buffer output, the watchdog feature is disabled. 3 - 4 /MR Manual Reset Input. A logic low on /MR asserts reset. Reset remains asserted as long as /MR is held low and for 200ms after /MR returns high. The active-low input has an internal 52k Ω pull-up resistor. It can be driven from a CMOS logic line or shorted to ground with a switch. Leave open or connect to VCC if unused. 5 5 5 VCC Supply Voltage Pin. VCC is the input to the supply voltage monitor. When the supply voltage falls below the reset threshold voltage, reset outputs (/RESET and RESET) are triggered immediately. When the supply voltage rises above the reset threshold plus hysteresis voltage, the reset outputs remain asserted for the duration of the reset timeout period. An optional 0.1µF bypass capacitor mounted close to VCC provides additional transient immunity. |
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