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MIC4605-1YMT Datasheet(PDF) 7 Page - Micrel Semiconductor |
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MIC4605-1YMT Datasheet(HTML) 7 Page - Micrel Semiconductor |
7 / 25 page Micrel, Inc. MIC4605 November 11, 2013 7 Revision 1.0 Timing Diagrams In LI/HI input mode, external LI/HI inputs are delayed to the point that HS is low before LI is pulled high and similarly LO is low before HI goes high HO goes high with a high signal on HI after a typical delay of 35ns (tHPLH). HI going low drives HO low also with typical delay of 35ns (tHPHL). Likewise, LI going high forces LO high after typical delay of 35ns (tLPLH) and LO follows low transition of LI after typical delay of 35ns (tLPHL). HO and LO output rise and fall times (tR/tF) are typically 20ns driving 1000pF capacitive loads. Note: All propagation delays are measured from the 50% voltage level. Figure 1. Separate Non-Overlapping LI/HI Input Mode (MIC4605-1) |
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