PH5551A2NA1-E4

Chapter Title

R08DS0037EJ0100 Rev.1.00

Page 6 of 10

Aug 03, 2011

2. Register Map

The register map is specified after the instruction code.

(1) Control Register

(a) Register Address: 000

0

0

0

0

0

0

0

0

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SWRST

INTCLR

INT_COND

RSLTN

INT_EN

*2

PWR

*1

Notes: *1 There are two PWR bits, one in the instruction code and one in the control register. When one bit changes,

the other bit also changes at the same time.

*2

There are two INT_EN bits in the control register. When one bit changes, the other bit also changes at the

same time.

SWRST

: Register reset (Initial values are restored by setting this bit to 1.)

INTCLR

: Interrupt source clear (1: Clear interrupt source)

INT_COND

: Interrupt result

(00: No comparison with threshold value; 01: Measured lux is lower than lower-limit threshold value;

11: Measured lux is higher than upper-limit threshold value.)

RSLTN

: Resolution selection (1 lx/16 lx) (0: 1 lx resolution; 1: 16 lx resolution)

INT_EN

: Interrupt enable/disable (1: Enable interrupts)

PWR

: Power on/Power down (1: Power on)

(b) Register Address: 001

0

0

0

0

0

0

0

0

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Lower interrupt generation threshold when interrupts are enabled - Lower 8 bits

(c) Register Address: 010

0

0

0

0

0

0

0

0

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Lower interrupt generation threshold when interrupts are enabled - Higher 8 bits

(d) Register Address: 011

0

0

0

0

0

0

0

0

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Upper interrupt generation threshold when interrupts are enabled - Lower 8 bits

(e) Register Address: 100

0

0

0

0

0

0

0

0

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Upper interrupt generation threshold when interrupts are enabled - Higher 8 bits