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EP2SGX30C Datasheet(PDF) 3 Page - Altera Corporation

Part # EP2SGX30C
Description  Stratix II GX Device Data Sheet
Download  326 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2SGX30C Datasheet(HTML) 3 Page - Altera Corporation

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Altera Corporation
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Contents
Section I. Stratix II GX Device Data Sheet
Chapter 1. Introduction
Features ................................................................................................................................................... 1–1
Referenced Document ........................................................................................................................... 1–5
Document Revision History ................................................................................................................. 1–5
Chapter 2. Stratix II GX Architecture
Transceivers ............................................................................................................................................ 2–1
Transmitter Path ............................................................................................................................... 2–4
Receiver Path ................................................................................................................................... 2–14
Loopback Modes ............................................................................................................................ 2–30
Transceiver Clocking ..................................................................................................................... 2–35
Other Transceiver Features ........................................................................................................... 2–41
Logic Array Blocks .............................................................................................................................. 2–44
LAB Interconnects .......................................................................................................................... 2–45
LAB Control Signals ....................................................................................................................... 2–46
Adaptive Logic Modules .................................................................................................................... 2–48
ALM Operating Modes ................................................................................................................. 2–50
Arithmetic Mode ............................................................................................................................ 2–55
Shared Arithmetic Mode ............................................................................................................... 2–58
Shared Arithmetic Chain ............................................................................................................... 2–60
Register Chain ................................................................................................................................. 2–61
Clear and Preset Logic Control .................................................................................................... 2–63
MultiTrack Interconnect ..................................................................................................................... 2–63
TriMatrix Memory ............................................................................................................................... 2–69
M512 RAM Block ............................................................................................................................ 2–70
M4K RAM Blocks ........................................................................................................................... 2–73
M-RAM Block ................................................................................................................................. 2–75
Digital Signal Processing (DSP) Block .............................................................................................. 2–81
Modes of Operation ....................................................................................................................... 2–85
DSP Block Interface ........................................................................................................................ 2–85
PLLs and Clock Networks .................................................................................................................. 2–89
Global and Hierarchical Clocking ................................................................................................2–89
Enhanced and Fast PLLs ............................................................................................................... 2–97
Enhanced PLLs ............................................................................................................................. 2–109
Fast PLLs ........................................................................................................................................ 2–109
I/O Structure ...................................................................................................................................... 2–110
Double Data Rate I/O Pins ......................................................................................................... 2–118
External RAM Interfacing ........................................................................................................... 2–122


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