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EL4585C Datasheet(PDF) 7 Page - Elantec Semiconductor |
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EL4585C Datasheet(HTML) 7 Page - Elantec Semiconductor |
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7 / 16 page  EL4585C Horizontal Genlock 8 FSC Description Of Operation Contd External Divide DIV SEL (pin 8) controls the use of the internal divider When high the internal divider is en- abled and EXT DIV (pin 13) outputs the CLK out divided by 2N This is the signal to which the horizontal sync input will lock When divide se- lect is low the internal divider output is disabled and external divide becomes an input from an ex- ternal divider so that a divisor other than one of the 8 pre-programmed internal divisors can be used Normal Mode Normal mode is enabled by pulling COAST (pin 9) low (below Vcc) If H-SYNC and CLKd2N have any phase or frequency difference an error signal is generated and sent to the charge pump The charge pump will either force current into or out of the filter capacitor in an attempt to modu- late the VCO frequency Modulation will contin- ue until the phase and frequency of CLKd2N exactly match the H-sync input When the phase and frequency match (with some offset in phase that is a function of the VCO characteristics) the error signal goes to zero lock detect no longer pulses high and the charge pump enters a high impedance state The clock is now locked to the H-sync input As long as phase and frequency differences remain small the PLL can adjust the VCO to remain locked and lock detect remains low Fast Lock Mode Fast Lock mode is enabled by either allowing coast to float or pulling it to mid supply (be- tween and Vcc) In this mode lock is achieved much faster than in normal mode but the clock divisor is modified on the fly to achieve this If the phase detector detects an error of enough magnitude the clock is either inhibited or reset to attempt a ‘‘fast lock’’ of the signals Forcing the clock to be synchronized to the H-sync input this way allows a lock in approxi- mately 2 H-cycles but the clock spacing will not be regular during this time Once the near lock condition is attained charge pump output should be very close to its lock-on value and placing the device into normal mode should result in a nor- mal lock very quickly Fast lock mode is intended to be used where H-sync becomes irregular until a stable signal is again obtained Coast Mode Coast mode is enabled by pulling COAST (pin 9) high (above Vcc) In coast mode the internal phase detector is disabled and filter out remains in high impedance mode to keep filter out volt- age and VCO frequency as constant a possible VCO frequency will drift as charge leaks from the filter capacitor and the voltage changes the VCO operating point Coast mode is intended to be used when noise or signal degradation result in loss of horizontal sync for many cycles The phase detector will not attempt to adjust to the resultant loss of signal so that when horizontal sync returns sync lock can be re-established quickly However if much VCO drift has oc- curred it may take as long to re-lock as when restarting Lock Detect Lock detect (pin 12) will go low when lock is es- tablished Any DC current path from charge pump out will skew EXT DIV relative to H- SYNC in tending to offset or add to the 110nS internal delay depending on which way the extra current is flowing This offset is called static phase error and is always present in any PLL system If when the part stabilizes in a locked mode lock detect is not low adding or subtract- ing from the loop filter series resistor R2 will change this static phase error to allow LDET to go low while in lock The goal is to put the rising edge of EXT DIV in sync with the falling edge of H-SYNC a 110nS (See timing diagrams) In- creasing R2 decreases phase error while decreas- ing R2 increases phase error (Phase error is posi- tive when EXT DIV lags H-SYNC) The resist- ance needed will depend on VCO design or VCXO module selection 7 |
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