10

EL7457C

40MHz Non-Inverting Quad CMOS Driver

Application Information:

Product Description

The EL7457C is a high performance 40MHz ultra-high

speed quad driver. Each channel of the EL7457C con-

sists of a single P-channel high side driver and a single

N-channel low side driver. These 3

Ω devices will pull

VH and VL respectively, depending on the input logic

of high and low voltage pins.

A common output enable (OE) pin is available on the

EL7457C. This pin, when pulled low will put all outputs

in to the high impedance state.

The EL7457C is available in both the 16-pin SOIC and

the space saving 16-pin QSOP packages. The relevant

package should be chosen depending on the calculated

power dissipation.

Supply Voltage Range and Input Compatibility

The EL7457C is designed for operation on supplies from

5V to 15V with 10% tolerance (i.e. 4.5V to 16.5V). The

table on page 6 shows the specifications for the relation-

EL7457C does not contain a true analog switch and

therefore VL should always be less than VH.

All input pins are compatible with both 3V and 5V

EL7457C is also compatible with TTL inputs.

Power Supply Bypassing

When using the EL7457C, it is very important to use

adequate power supply bypassing. The high switching

currents developed by the EL7457C necessitate the use

of a bypass capacitor on both the positive and negative

supplies. It is recommended that a 4.7µ F tantalum

capacitor be used in parallel with a 0.1µ F low-induc-

tance ceramic MLC capacitor. These should be placed as

close to the supply pins as possible. It is also recom-

mended that the VH and VL pins have some level of

bypassing, especially if the EL7457C is driving highly

capacitive loads.

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads,

the EL7457C drive capability is limited by the rise in die

temperature brought about by internal power dissipation.

For reliable operation die temperature must be kept

power dissipation for a given application prior to select-

ing the package type.

Power dissipation may be calculated:

where:

• f is frequency

Having obtained the application’s power dissipation, a

maximum package thermal coefficient may be deter-

mined, to maintain the internal die temperature below

where:

• PD is the power dissipation calculated above.

Using the value of

tion may be selected.

In applications with a

QSOP may be used. A 16-pin SOIC is suitable for appli-

cations with a

PD

V

S

I

S

×

()

C

INT

V

S

2

×

f

×

()

C

L

V

OUT

2

×

f

×

()

+

1

4

∑

+

=

θ

ja

T

jmax

T

max

–

()

PD

----------------------------------------

=