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EL7571C Datasheet(PDF) 7 Page - Elantec Semiconductor |
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EL7571C Datasheet(HTML) 7 Page - Elantec Semiconductor |
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7 / 23 page  7 EL7571C Programmable PWM Controller Applications Information Circuit Description General The EL7571C is a fixed frequency, current mode, pulse width modulated (PWM) controller with an integrated high precision reference and a 5 bit Digital-to-Analog Converter (DAC). The device incorporates all the active circuitry required to implement a synchronous step down (buck) converter which conforms to the Intel Pen- tium® II VRM specification. Complementary switching outputs are provided to drive dual NMOS power FET’s in either synchronous or non-synchronous configura- tions, enabling the user to realize a variety of high efficiency and low cost converters. Reference A precision, temperature compensated band gap refer- ence forms the basis of the EL7571C. The reference is trimmed during manufacturing and provides 1% set point accuracy for the overall regulator. AC rejection of the reference is optimized using an external bypass capacitor CREF. Main Loop A current mode PWM control loop is implemented in the EL7571C (see block diagram). This configuration employs dual feedback loops which provide both output voltage and current feedback to the controller. The resulting system offers several advantages over traditi- tional voltage control systems, including simpler loop design, pulse by pulse current limiting, rapid response to line variaion and good load step response. Current feed- back is performed by sensing voltage across an external shunt resistor. Selection of the shunt resistance value sets the level of current feedback and thereby the load regulation and current limit levels. Consequently, opera- tion over a wide range of output currents is possible. The reference output is fed to a 5 bit DAC with step weigh- ing conforming to the Intel VRM Specification. Each DAC input includes an internal current pull up which directly interfaces to the VID output of a Pentium® II class microprocessor. The heart of the controller is a tri- ple-input direct summing differential comparator, which sums voltage feedback, current feedback and compen- sating ramp signals together. The relative gains of the comparator input stages are weighed. The ratio of volt- age feedback to current feedback to compensating ramp defines the load regulation and open loop voltage gain for the system, respectively. The compensating ramp is required to maintain large system signal system stability for PWM duty cycles greater than 50%. Compensation ramp amplitude is user adjustable and is set with a single external capacitor (CSLOPE). The ramp voltage is ground referenced and is reset to ground whenever the high side drive signal is low. In operation, the DAC out- put voltage is compared to the regulator output, which has been internally attenuated. The resulting error volt- age is compared with the compensating ramp and current feedback voltage. PWM duty cycle is adjusted by the comparator output such that the combined com- parator input sums to zero. A weighted comparator scheme enhances system operation over traditional volt- age error amplifier loops by providing cycle-by-cycle adjustment of the PWM output voltage, eliminating the need for error amplifier compensation. The dominant pole in the loop is defined by the output capacitance and equivalent load resistance, the effect of the output induc- tor having been canceled due to the current feedback. An output enable (OUTEN) input allows the regulator out- put to be disabled by an external logic control signal. Auxiliary Comparators The current feedback signal is monitored by two addi- tional comparators which set the operating limits for the main inductor current. An over current comparator ter- minates the PWM cycle independently of the main summing comparator output whenever the voltage across the sense resistor exceeds 154mV. For a 7.5m Ω resistor this corresponds to a nominal 20A current limit. Since output current is continuously monitored, cycle- by-cycle current limiting results. A second comparator senses inductor current reverse flow. The low side drive signal is terminated when the sense resistor voltage is less than -5mV, corresponding to a nominal reverse cur- rent of -0.67A, for a 7.5m Ω sense resistor. Additionally, under fault conditions, with the regulator output over- |
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