4

EL7564C

Monolithic 4 Amp DC:DC Step-down Regulator

Pin Descriptions

Pin Number

Pin Name

Pin Function

1

VREF

Bandgap reference bypass capacitor; typically 0.1µF to SGND

2

SGND

Control circuit negative supply or signal ground

3

COSC

Oscillator timing capacitor (see performance curves)

4

VDD

Control circuit positive supply; normally connected to VIN through an RC filter

5

VTJ

Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND

6

PGND

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

7

PGND

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

8

VIN

Power supply input of the regulator; connected to the drain of the high-side NMOS power FET

9

STP

Auxilliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open

for stand alone operation; 2µA internal pull down current

10

STN

Auxilliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for

stand alone operation; 2µA internal pull up current

11

PGND

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

12

PGND

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

13

PGND

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

14

LX

Inductor drive pin; high current output whose average voltage equals the regulator output voltage

15

LX

Inductor drive pin; high current output whose average voltage equals the regulator output voltage

16

VHI

Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF capacitor

17

VDRV

Positive supply of low-side driver and input voltage for high side boot strap

18

PG

Power good window comparator output; logic 1 when regulator output is within ±10% of target output voltage

19

FB

Voltage feedback input; connected to external resistor divider between VOUT and SGND; a 125nA pull-up current forces

VOUT to SGND in the event that FB is floating

20

EN

Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open; a capacitor can be added

at this pin to delay the start of converter