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NAND512R3A2C Datasheet(PDF) 6 Page - Numonyx B.V |
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NAND512R3A2C Datasheet(HTML) 6 Page - Numonyx B.V |
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6 / 55 page  Description NAND512-A2C 6/55 1 Description The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that uses the single level cell (SLC) NAND technology. It is referred to as the small page family. The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512 Mbits and operate with either a 1.8 V or 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. To extend the lifetime of NAND flash devices it is strongly recommended to implement an error correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A write protect pin is available to give a hardware protection against program and erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the program/erase/read (P/E/R) controller is currently active. The use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. The devices are available in the TSOP48 (12 x 20 mm), VFBGA55 (8 x 10 x 1.05 mm) and VFBGA63 (9 x 11 x 1.05 mm) packages and in two different versions: ● No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read feature allows to download up to all the pages in a block with one read command and addressing only the first page to read ● With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between more active memories that are simultaneously active as Chip Enable transitions during latency do not stop read operations. Program and erase operations are not interrupted by Chip Enable transitions. They also come with the following security features: ● OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently. The access sequence and further details about this feature are subject to an NDA (non disclosure agreement) ● Serial number (unique identifier) option, which enables each device to be uniquely identified. It is subject to an NDA and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. For information on how to order these devices refer to Table 25: Ordering information scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’1’. See Table 2: Product description, for all the devices available in the family. |
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