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EL7564CRE-T7 Datasheet(PDF) 10 Page - Elantec Semiconductor |
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EL7564CRE-T7 Datasheet(HTML) 10 Page - Elantec Semiconductor |
10 / 18 page 10 EL7564C Monolithic 4 Amp DC:DC Step-down Regulator high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. However, the maximum on-duty ratio of the high-side switch is limited to 95%. In order to eliminate cross-con- duction of the high-side and low-side switches a 15ns break-before-make delay is incorporated in the switch drive circuitry. The output enable (EN) input allows the regulator output to be disabled by an external logic con- trol signal. Output Voltage Setting In general: However, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loop-gain is changed. This is shown in the performance curves. A 100nA pull-up current from FB to VDD forces VOUT to GND in the event that FB is floating. NMOS Power FETs and Drive Circuitry The EL7564C integrates low on-resistance (30m Ω) NMOS FETs to achieve high efficiency at 4A. In order to use an NMOS switch for the high-side drive it is nec- essary to drive the gate voltage above the source voltage (LX). This is accomplished by bootstrapping the VHI pin above the LX voltage with an external capacitor CVHI and internal switch and diode. When the low-side switch is turned on and the LX voltage is close to GND potential, capacitor CVHI is charged through internal switch to VDRV, typically 5V. At the beginning of the next cycle the high-side switch turns on and the LX pins begin to rise from GND to VIN potential. As the LX pin rises the positive plate of capacitor CVHI follows and eventually reaches a value of VDRV+VIN, typically 10V, for VDRV=VIN=5V. This voltage is then level shifted and used to drive the gate of the high-side FET, via the VHI pin. A value of 0.22µF for CVHI is recommended. Reference A 1.5% temperature compensated bandgap reference is integrated in the EL7564C. The external VREF capaci- tor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. A value of 0.1µF is recommended. Oscillator The system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 95%. Operating frequency can be adjusted through the COSC pin or can be driven by an external source. If the oscillator is driven by an external source care must be taken in selecting the ramp amplitude. Since CSLOPE value is derived from the COSC ramp, changes to COSC ramp will change the CSLOPE compensation ramp which determine the open-loop gain of the system. When external synchronization is required, always choose COSC such that the free-running frequency is at least 20% lower than that of sync source to accommo- date component and temperature variations. Figure 1 shows a typical connection. Junction Temperature Sensor An internal temperature sensor continuously monitors die temperature. In the event that die temperature exceeds the thermal trip-point, the system is in fault state and will be shut down. The upper and low trip-points are set to 135°C and 115°C respectively. The VTJ pin is an accurate indication of the internal sili- con junction temperature (see performance curve.) The VOUT 0.975V 1 R2 R1 ------ + × = 2 3 16 15 14 13 5 6 7 12 11 9 8 10 19 18 EL7564C 1 20 External Oscillator BAT54S 100pF 390pF Figure 1. Oscillator Synchronization |
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