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EBS12UC6APS-75L Datasheet(PDF) 5 Page - Elpida Memory |
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EBS12UC6APS-75L Datasheet(HTML) 5 Page - Elpida Memory |
5 / 14 page EBS12UC6APS Data Sheet E0224E20 (Ver. 2.0) 5 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 28 Row active to row active min (-7A/7AL, -75/75L) 0 0 0 0 1 1 1 1 0FH 15ns (-80/80L) 0 0 0 1 0 0 0 0 10H 16ns 29 /RAS to /CAS delay min (-7A/7AL) 0 0 0 0 1 1 1 1 0FH 15ns (-75/75L, -80/80L) 0 0 0 1 0 1 0 0 14H 20ns 30 Minimum /RAS pulse width (-7A/7AL, -75/75L) 0 0 1 0 1 1 0 1 2DH 45ns (-80/80L) 0 0 1 1 0 0 0 0 30H 48ns 31 Density of each bank on module 0 0 1 0 0 0 0 0 20H 128MB 32 Address and command signal input setup time (-7A/7AL, -75/75L) 0 0 0 1 0 1 0 1 15H 1.5ns (-80/80L) 0 0 1 0 0 0 0 0 20H 2ns 33 Address and command signal input hold time (-7A/7AL, -75/75L) 0 0 0 0 1 0 0 0 08H 0.8ns (-80/80L) 0 0 0 1 0 0 0 0 10H 1ns 34 Data signal input setup time (-7A/7AL, -75/75L) 0 0 0 1 0 1 0 1 15H 1.5ns (-80/80L) 0 0 1 0 0 0 0 0 20H 2ns 35 Data signal input hold time (-7A/7AL, -75/75L) 0 0 0 0 1 0 0 0 08H 0.8ns (-80/80L) 0 0 0 1 0 0 0 0 10H 1ns 36 to 61 Superset information 0 0 0 0 0 0 0 0 00H 62 SPD data revision code 0 0 0 1 0 0 1 0 12H 1.2 63 Checksum for Bytes 0 to 62 (-7A/7AL) 0 1 1 1 1 0 0 0 78H (-75/75L) 1 0 1 1 1 0 0 1 B9H (-80/80L) 1 1 1 1 1 0 1 0 FAH 64 Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0 FEH Elpida Memory 65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00H 72 Manufacturing location 73 to 90 Manufacturer’s part number 91 to 92 Revision code 93 to 94 Manufacturing date 95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 Reserved (Intel specification frequency) 0 1 1 0 0 1 0 0 64H 100MHz 127 Reserved (Intel specification /CAS# latency support) 1 1 0 0 0 1 1 1 C7H |
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