EBS52EC8APFA

Data Sheet E0207E20 (Ver. 2.0)

9

Pin Capacitance (TA = 25°C, VDD = 3.3V ± 0.3V)

Parameter

Symbol

Pins

max.

Unit

Notes

Input capacitance

CI1

Address

TBD

pF

CI2

/RAS, /CAS, /WE

TBD

pF

CI3

CKE

TBD

pF

CI4

/CS

TBD

pF

CI5

CLK

TBD

pF

CI6

DQMB

TBD

pF

Data input/output capacitance

CI/O1

DQ, CB

TBD

pF

AC Characteristics (TA = 0 to 70°C, VDD = 3.3V ± 0.3V, VSS = 0V) (SDRAM device specification)

-7A

-75

Parameter

Symbol

min.

min.

max.

Unit

Notes

System clock cycle time

tCK

7.5

7.5

—

ns

1

CLK high pulse width

tCH

2.5

2.5

—

ns

1

CLK low pulse width

tCL

2.5

2.5

—

ns

1

Access time from CLK

tAC

—

—

5.4

ns

1, 2

Data-out hold time

tOH

2.7

2.7

—

ns

1, 2

CLK to Data-out low impedance

tLZ

1

1

—

ns

1, 2, 3

CLK to Data-out high impedance

tHZ

—

—

5.4

ns

1, 4

Input setup time

tSI

1.5

1.5

—

ns

1

Input hold time

tHI

0.8

0.8

—

ns

1

Ref/Active to Ref/Active command period tRC

60

67.5

—

ns

1

Active to Precharge command period

tRAS

45

45

120000

ns

1

Active command to column command

(same bank)

tRCD

15

20

—

ns

1

Precharge to active command period

tRP

15

20

—

ns

1

Write recovery or data-in to precharge

lead time

tDPL

15

15

—

ns

1

Last data into active latency

tDAL

2CLK + 15ns

2CLK + 20ns

—

Active (a) to Active (b) command period

tRRD

15

15

—

ns

1

Transition time (rise and fall)

tT

0.5

0.5

5

ns

Refresh period

(8192 refresh cycles)

tREF

—

—

64

ms

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.