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HB52E649E12-A6B Datasheet(PDF) 4 Page - Elpida Memory |
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HB52E649E12-A6B Datasheet(HTML) 4 Page - Elpida Memory |
4 / 16 page HB52E649E12-A6B/B6B Data Sheet E0020H20 4 Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 36 A6 78 V SS 120 A7 162 V SS 37 A8 79 CK2 121 A9 163 CK3 38 A10 (AP) 80 NC 122 BA0 164 NC 39 BA1 81 WP 123 A11 165 SA0 40 V CC 82 SDA 124 V CC 166 SA1 41 V CC 83 SCL 125 CK1 167 SA2 42 CK0 84 V CC 126 A12 168 V CC Pin Description Pin name Function A0 to A12 Address input Row address A0 to A12 Column address A0 to A9, A11 BA0/BA1 Bank select address DQ0 to DQ63 Data input/output CB0 to CB7 Check bit (Data input/output) S0, S2 Chip select input RE Row enable (RAS) input CE Column enable (CAS) input W Write enable input DQMB0 to DQMB7 Byte data mask CK0 to CK3 Clock input CKE0 Clock enable input WP Write protect for serial PD REGE* 1 Register/Buffer enable SDA Data input/output for serial PD SCL Clock input for serial PD SA0 to SA2 Serial address input V CC Primary positive power supply V SS Ground NC No connection Note: 1. REGE ≥ V IH: Register mode. REGE ≤ V IL: Buffer mode. |
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