EDS2516APSA-7AL datasheet(6/51 Pages) ELPIDA

Part #	EDS2516APSA-7AL

Description	256M bits SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

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EDS2508APSA, EDS2516APSA

Data Sheet E0228E30 (Ver. 3.0)

6

Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)

Parameter

Symbol

Pins

min.

Typ

max.

Unit

Notes

Input capacitance

CI1

CLK

2.0

—

3.5

pF

1, 2, 4

CI2

Address, CKE, /CS, /RAS,

/CAS, /WE, DQM,

2.0

—

3.8

pF

1, 2, 4

Data input/output capacitance

CI/O

DQ

4

—

6.5

pF

1, 2, 3, 4

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.

3. DQM = VIH to disable DOUT.

4. This parameter is sampled and not 100% tested.

AC Characteristics (TA = 0 to +70

°°°°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)

-7A

-75

Parameter

Symbol

min.

max.

min.

max.

Unit

Notes

System clock cycle time

tCK

7.5

—

7.5

—

ns

1

CLK high pulse width

tCH

2.5

—

2.5

—

ns

1

CLK low pulse width

tCL

2.5

—

2.5

—

ns

1

Access time from CLK

tAC

—

5.4

—

5.4

ns

1, 2

Data-out hold time

tOH

3.0

—

3.0

—

ns

1, 2

CLK to Data-out low impedance

tLZ

1

—

1

—

ns

1, 2, 3

CLK to Data-out high impedance

tHZ

—

5.4

—

5.4

ns

1, 4

Input setup time

tSI

1.5

—

1.5

—

ns

1

Input hold time

tHI

0.8

—

0.8

—

ns

1

Ref/Active to Ref/Active command

period

tRC

60

—

67.5

—

ns

1

Active to Precharge command

period

tRAS

45

120000

45

120000

ns

1

Active command to column

command (same bank)

tRCD

15

—

20

—

ns

1

Precharge to active command

period

tRP

15

—

20

—

ns

1

Write recovery or data-in to

precharge lead time

tDPL

15

—

15

—

ns

1

Last data into active latency

tDAL

2CLK +

15ns

—

2CLK +

20ns

—

Active (a) to Active (b) command

period

tRRD

15

—

15

—

ns

1

Transition time (rise and fall)

tT

0.5

5

0.5

5

ns

Refresh period

(8192 refresh cycles)

tREF

—

64

—

64

ms

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

2. Access time is measured at 1.4V. Load condition is CL = 50pF.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.

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