Document No. E0223H30 (Ver. 3.0)

Date Published April 2002 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2001-2002

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

DATA SHEET

512MB Unbuffered SDRAM S.O.DIMM

HB52RF649DC-B (64M words

×××× 72 bits, 2 bank)

HB52RD649DC-B (64M words

×××× 72 bits, 2 bank)

Description

The HB52RF649DC, HB52RD649DC are a 64M

× 72 ×

2 banks Synchronous Dynamic RAM Small Outline

Dual In-line Memory Module (S.O.DIMM), mounted 18

pieces of 256M bits SDRAM sealed in TCP package

and 1 piece of serial EEPROM (2k bits) for Presence

Detect (PD). An outline of the products is 144-pin Zig

Zag Dual tabs socket type compact and thin package.

Therefore, they make high density mounting possible

without surface mount technology.

They provide

common

data

inputs

and

outputs.

Decoupling

capacitors are mounted beside TCP on the module

board.

Note: Do not push the cover or drop the modules in

order to protect from mechanical defects, which

would be electrical defects.

Features

• Fully compatible with: JEDEC standard outline 8

bytes S.O.DIMM

• 144-pin Zig Zag Dual tabs socket type (dual lead out)

 PCB height: 33.02mm (1.30inch)

 Lead pitch: 0.80mm

• 3.3V power supply

• Clock frequency: 133MHz/100MHz (max.)

• LVTTL interface

• Data bus width: × 72 ECC

• Single pulsed /RAS

• 4 Banks can operates simultaneously and

independently

• Burst read/write operation and burst read/single write

operation capability

• Programmable burst length (BL): 1, 2, 4, 8

• 2 variations of burst sequence

 Sequential

 Interleave

• Programmable /CE latency (CL): 2, 3

• Byte control by DQMB

• Refresh cycles: 8192 refresh cycles/64ms

• 2 variations of refresh

 Auto refresh

 Self refresh

• Low self refresh current

: HB52RF649DC-xxBL (L-version)

: HB52RD649DC-xxBL (L-version)