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ISP1761BEUM Datasheet(PDF) 8 Page - NXP Semiconductors |
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ISP1761BEUM Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 164 page  ISP1761_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 13 March 2008 7 of 163 NXP Semiconductors ISP1761 Hi-Speed USB OTG controller 6.2 Pin description Table 2. Pin description Symbol[1][2] Pin Type[3] Description LQFP128 TFBGA128 OC3_N 1 C2 AI/I port 3 analog (5 V input) and digital overcurrent input; if not used, connect to VCC(I/O) through a 10 kΩ resistor input, 5 V tolerant REF5V 2 A2 AI 5 V reference input for analog OC detector; connect a 100 nF decoupling capacitor ID 3 B2 I ID input to detect the default host or peripheral setting when port 1 is in OTG mode; pull-up to 3.3 V through a 4.7 k Ω resistor input, 3.3 V tolerant GNDA 4 A1 - analog ground REG1V8 5 B1 P core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor; for details on additional capacitor placement, see Section 7.7 VCC(5V0) 6 C1 P input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF decoupling capacitor; see Section 7.7 VCC(5V0) 7 D2 P input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF decoupling capacitor; see Section 7.7 GND(OSC) 8 E3 - oscillator ground REG3V3 9 D1 P regulator output (3.3 V); for decoupling only; connect a 100 nF capacitor and a 4.7 µF-to-10 µF capacitor; see Section 7.7 VCC(I/O) 10 E2 P digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 XTAL1 11 E1 AI 12 MHz crystal connection input; connect to ground if an external clock is used XTAL2 12 F2 AO 12 MHz crystal connection output CLKIN 13 F1 I 12 MHz oscillator or clock input; when not in use, connect to VCC(I/O) GNDD 14 G3 - digital ground GND(RREF1) 15 G2 - RREF1 ground RREF1 16 G1 AI reference resistor connection; connect a 12 k Ω± 1 % resistor between this pin and the RREF1 ground GNDA[4] 17 H2 - analog ground DM1 18 H1 AI/O downstream data minus port 1 GNDA 19 J3 - analog ground DP1 20 J2 AI/O downstream data plus port 1 PSW1_N 21 J1 OD power switch port 1, active LOW output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant GND(RREF2) 22 K2 - RREF2 ground RREF2 23 K1 AI reference resistor connection; connect a 12 k Ω± 1 % resistor between this pin and the RREF2 ground GNDA[5] 24 L3 - analog ground DM2 25 L1 AI/O downstream data minus port 2 GNDA 26 L2 - analog ground DP2 27 M2 AI/O downstream data plus port 2 |
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