ISP1761BEUM datasheet(2/164 Pages) PHILIPS

Part #	ISP1761BEUM

Description	Hi-Speed Universal Serial Bus On-The-Go controller

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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1.

General description

The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)

Controller integrated with advanced NXP slave host controller and the NXP ISP1582

peripheral controller.

The Hi-Speed USB host controller and peripheral controller comply to Ref. 1 “Universal

Serial Bus Speciﬁcation Rev. 2.0” and support data transfer speeds of up to 480 Mbit/s.

The Enhanced Host Controller Interface (EHCI) core implemented in the host controller is

adapted from Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for Universal Serial

Bus Rev. 1.0”. The OTG controller adheres to Ref. 3 “On-The-Go Supplement to the USB

Speciﬁcation Rev. 1.3”.

The ISP1761 has three USB ports. Port 1 can be conﬁgured to function as a downstream

port, an upstream port or an OTG port; ports 2 and 3 are always conﬁgured as

downstream ports. The OTG port can switch its role from host to peripheral, and

peripheral to host. The OTG port can become a host through the Host Negotiation

Protocol (HNP) as speciﬁed in the OTG supplement.

2.

Features

I Compliant with Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”; supporting data

transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

I Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)

peripheral support

I Three USB ports that support three operational modes:

N Mode 1: Port 1 is an OTG controller port, and ports 2 and 3 are host controller

ports

N Mode 2: Ports 1, 2 and 3 are host controller ports

N Mode 3: Port 1 is a peripheral controller port, and ports 2 and 3 are host controller

ports

I Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

I Multitasking support with virtual segmentation feature (up to four banks)

I High-speed memory controller (variable latency and SRAM external interface)

I Directly addressable memory architecture

I Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,

Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC

Reduced Instruction Set Computer (RISC) processors

I Conﬁgurable 32-bit and 16-bit external memory data bus

I Supports Programmed I/O (PIO) and Direct Memory Access (DMA)

I Slave DMA implementation on CPU interface to reduce the host system’s CPU load

ISP1761

Hi-Speed Universal Serial Bus On-The-Go controller

Rev. 05 — 13 March 2008

Product data sheet

Similar Part No. - ISP1761BEUM

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	ISP1761BE	724Kb / 158P	Hi-Speed Universal Serial Bus On-The-Go controller Rev. 01-12 January 2005

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ISP1761BEUM Datasheet(PDF) 2 Page - NXP Semiconductors

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