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EDS2516APTA-75 Datasheet(PDF) 5 Page - Elpida Memory

Part # EDS2516APTA-75
Description  256M bits SDRAM
Download  51 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS2516APTA-75 Datasheet(HTML) 5 Page - Elpida Memory

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EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Data Sheet E0110E30 (Ver. 3.0)
5
DC Characteristics 1 (TA = 0 to +70
°°°°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
max.
/CAS latency
Symbol
Grade
× 4
× 8
× 16
Unit
Test condition
Notes
Operating current
ICC1
-7A
130
130
135
mA
Burst length = 1
tRC = min.
1, 2, 3
ICC1
-75
110
110
115
mA
Burst length = 1
tRC = min.
Standby current in power
down
ICC2P
3
3
3
mA
CKE = VIL, tCK = min.
6
Standby current in power
down (input signal stable)
ICC2PS
2
2
2
mA
CKE = VIL, tCK =
∞
7
Standby current in power
down (input signal stable)
(EDS2504AP/08AP/16AP)
(L-version)
ICC2PS
-XXL
0.5
0.5
0.5
mA
CKE = VIL, tCK =
∞
9
Standby current in non
power down
ICC2N
20
20
20
mA
CKE, /CS = VIH,
tCK = min.
4
Standby current in non
power down (input signal
stable)
ICC2NS
9
9
9
mA
CKE = VIH, tCK =
∞,
/CS = VIH
8
Active standby current in
power down
ICC3P
4
4
4
mA
CKE = VIL, tCK = min.
1, 2, 6
Active standby current in
power down (input signal
stable)
ICC3PS
3
3
3
mA
CKE = VIL, tCK =
∞
2, 7
Active standby current in
non power down
ICC3N
30
30
30
mA
CKE, /CS = VIH,
tCK = min.
1, 2, 4
Active standby current in
non power down (input
signal stable)
ICC3NS
15
15
15
mA
CKE = VIH, tCK =
∞,
/CS = VIH
2, 8
Burst operating current
ICC4
130
135
145
mA
tCK = min., BL = 4
1, 2, 5
Refresh current
ICC5
-7A
250
250
250
mA
tRC = min.
3
ICC5
-75
220
220
220
mA
tRC = min.
Self refresh current
ICC6
3
3
3
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Self refresh current
(EDS2504AP/08AP/16AP)
(L-version)
ICC6
-XXL
1
1
1
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
9
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
9. This characteristic is guaranteed only for EDS2504AP/08AP/16AP (L-version).


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