EDS2504APTA-7AL datasheet(7/51 Pages) ELPIDA

Part #	EDS2504APTA-7AL

Description	256M bits SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

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EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA

Data Sheet E0110E30 (Ver. 3.0)

7

Test Conditions

• Input and output timing reference levels: 1.4V

• Input waveform and output load: See following figures

tT

2.4 V

0.4 V

0.8 V

2.0 V

input

tT

I/O

CL

Output load

Relationship Between Frequency and Minimum Latency

Parameter

-7A

-75

Frequency (MHz)

133

tCK (ns)

Symbol

7.5

Notes

Active command to column command

(same bank)

lRCD

2

3

1

Active command to active command

(same bank)

lRC

8

9

1

Active command to precharge command

(same bank)

lRAS

6

1

Precharge command to active command

(same bank)

lRP

2

3

1

Write recovery or data-in to precharge

command (same bank)

lDPL

2

1

Active command to active command

(different bank)

lRRD

2

1

Self refresh exit time

lSREX

1

2

Last data in to active command

(Auto precharge, same bank)

lDAL

4

5

= [lDPL + lRP]

Self refresh exit to command input

lSEC

8

9

= [lRC]

3

Precharge command to high impedance

(CL = 2)

lHZP

2

(CL = 3)

lHZP

3

Last data out to active command

(auto precharge) (same bank)

lAPR

1

Last data out to precharge (early precharge)

(CL = 2)

lEP

–1

(CL = 3)

lEP

–2

Column command to column command

lCCD

1

Write command to data in latency

lWCD

0

DQM to data in

lDID

0

DQM to data out

lDOD

2

CKE to CLK disable

lCLE

1

Register set to active command

lMRD

2

4

/CS to command disable

lCDD

0

Power down exit to command input

lPEC

1

Notes: 1.IRCD to IRRD are recommended value.

2. Be valid [DESL] or [NOP] at next command of self refresh exit.

3. Except [DESL] and [NOP]

4. EDS2504AC/08AC/16AC is possible lMRD 1 clock.

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