HM5259165B-A6 datasheet(11/63 Pages) ELPIDA

Part #	HM5259165B-A6

Description	512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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11 / 63 page

HM5259165B/HM5259805B/HM5259405B-75/A6

Data Sheet E0118H10

11

Column address strobe and write command [WRIT]: This command starts a write operation. When the

burst write mode is selected, the column address (AY0 to AY9; HM5259165B, AY0 to AY9, AY11;

HM5259805B, AY0 to AY9, AY11, AY12; HM5259405B) and the bank select address (BA0/BA1) become

the burst write start address. When the single write mode is selected, data is only written to the location

specified by the column address (AY0 to AY9; HM5259165B, AY0 to AY9, AY11; HM5259805B, AY0 to

AY9, AY11, AY12; HM5259405B) and the bank select address (BA0/BA1).

Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a

burst write with a length of 1, 2, 4 or 8, or after a single write operation.

Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by

BA0/BA1 (BS) and determines the row address (AX0 to AX12). When BA0 and BA1 are Low, bank 0 is

activated. When BA0 is Low and BA1 is High, bank 1 is activated. When BA0 is High and BA1 is Low,

bank 2 is activated. When BA0 and BA1 are High, bank 3 is activated.

Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by

BA0/BA1. If BA0 and BA1 are Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected.

If BA0 is High and BA1 is Low, bank 2 is selected. If BA0 and BA1 are High, bank 3 is selected.

Precharge all banks [PALL]: This command starts a precharge operation for all banks.

Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,

the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.

Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register

is specified by the address pins (A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the

mode register configuration. After power on, the contents of the mode register are undefined, execute the

mode register set command to set up the mode register.

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HM5259165B-A6 Datasheet(PDF) 11 Page - Elpida Memory

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