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M1A3P1000L Datasheet(PDF) 1 Page - Microsemi Corporation |
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M1A3P1000L Datasheet(HTML) 1 Page - Microsemi Corporation |
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1 / 242 page  January 2013 I © 2013 Microsemi Corporation ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • Dramatic Reduction in Dynamic and Static Power Savings • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Allows for Instantaneous Entry to / Exit from Low-Power Flash*Freeze Mode • Supports Single-Voltage System Operation • Low-Impedance Switches High Capacity • 250,000 to 3,000,000 System Gates • Up to 504 kbits of True Dual-Port SRAM • Up to 620 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process • Instant On Level 0 Support • Single-Chip Solution • Retains Programmed Design when Powered Off High Performance • 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System Performance • 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit PCI (1.2 V systems) In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant) • FlashLock® to Secure FPGA Contents High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization Advanced and Pro (Professional) I/Os • 700 Mbps DDR, LVDS-Capable I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 8 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS • Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II (A3PE3000L only) • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os Programmable Output Slew Rate and Drive Strength • Programmable Input Delay (A3PE3000L only) • Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L) • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the ProASIC®3L Family (except PQ208) Clock Conditioning Circuit (CCC) and PLL • Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All with Integrated PLL (ProASIC3EL) • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V systems) and 350 MHz (1.5 V systems)) SRAMs and FIFOs • Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available) • True Dual-Port SRAM (except ×18) • 24 SRAM and FIFO Configurations with Synchronous Operation: – 250 MHz: For 1.2 V systems – 350 MHz: For 1.5 V systems ARM® Processor Support in ProASIC3L FPGAs • ARM Cortex™-M1 Soft Processor Available with or without Debug Table 1 • ProASIC3 Low-Power Product Family ProASIC3L Devices A3P250L A3P600L A3P1000L A3PE3000L ARM Cortex-M1 Devices 1 M1A3P600L M1A3P1000L M1A3PE3000L System Gates 250,000 600,000 1,000,000 3,000,000 VersaTiles (D-flip-flops) 6,144 13,824 24,576 75,264 RAM Kbits (1,024 bits) 36 108 144 504 4,608-Bit Blocks 824 32 112 FlashROM Kbits 111 1 Secure (AES) ISP 2 Yes Yes Yes Yes Integrated PLL in CCCs 3 111 6 VersaNet Globals 18 18 18 18 I/O Banks 444 8 Maximum User I/Os 157 235 300 620 Package Pins VQFP PQFP FBGA VQ100 PQ208 FG144, FG256 PQ208 FG144, FG256, FG484 PQ208 FG144, FG256, FG484 PQ208 3 FG324, FG484, FG896 Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. AES is not available for ARM Cortex-M1 ProASIC3L devices. 3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs. Revision 13 |
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